LOUISVILLE, Colo. – December 12, 2011 -- The Design Automation Conference (DAC), the premier event on automation and design of electronic systems, announces its first ever EDA algorithm competition. The results will be announced two weeks prior to the 49th DAC, which will be held at the Moscone Center in San Francisco, California, from June 3-7, 2012. Awards will be presented at a ceremony during DAC. Prize money will be distributed among the highest performing teams.
Creating easily routable designs is one of the key challenges for modern physical synthesis design closure tools. Numerous factors contribute to making this problem increasingly challenging with advanced process technologies. Increased (re)use of embedded IPs or memories that complicate placement and block wiring channels, non-uniform metal layer stacks designed for higher performance, the pressure to reduce die size to control manufacturing cost, and ever increasingly complex design rules. Consequently, the design closure flow needs to be aware of routability during the entire flow, especially during cell placement.
Recent years have seen significant advances in wirelength-driven placement; however, wirelength does not directly correspond with design routability. The problem is exacerbated by the lack of standard frameworks and metrics to evaluate the routability of a given placement. To help further advance the state-of-the-art in placement, DAC is sponsoring its first contest on the topic of routability-driven placement.
“Contestants will be evaluated on the routability of their solutions as determined by a global routing based contest evaluation tool,” said Natarajan Viswanathan of IBM Corporation, the contest administrator. “The quality of the solution will be measured on wire length, and various measures of global and local routing congestion.”
To participate, contestant teams must register by December 30th 2011. Please visit /routability_driven+placement+contest.aspx for full details of the competition and to register.
The Design Automation Conference (DAC) is recognized as the premier event for the design of electronic circuits and systems, and for electronic design automation (EDA) and silicon solutions. A diverse worldwide community representing more than 1,000 organizations attends each year, represented by system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities. Close to 60 technical sessions selected by a committee of electronic design experts offer information on recent developments and trends, management practices and new products, methodologies and technologies. A highlight of DAC is its exhibition and suite area with approximately 200 of the leading and emerging EDA, silicon, intellectual property (IP) and design services providers. The conference is sponsored by the Association for Computing Machinery (ACM), the Electronic Design Automation Consortium (EDA Consortium), and the Institute of Electrical and Electronics Engineers (IEEE), and is supported by ACM's Special Interest Group on Design.
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