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"Wild and Crazy Ideas" (WACI)

"Wild and Crazy Ideas" (WACI) 
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The WACI sessions feature novel (and even preliminary or unproven) technical ideas.

DAC invites submissions with genuinely forward-looking, radical, and innovative ideas in the area of electronic design or electronic design automation.  

The aim of WACI is to promote revolutionary and way-out ideas that do not fit the conventional mold, that inspire discussion among conference attendees, that create a buzz, and that get people talking. Research that incrementally improves on prior work is not suited for this category.

Unlike a DAC research manuscript that explores a specific technology problem and proposes a complete solution to it, with extensive experimental results, a WACI paper could present less developed but highly innovative ideas related to areas relevant to DAC.

All WACI accepted manuscripts will be required to post a two-minute video describing the work as part of the acceptance process. See 2011 WACI videos

New SUBMISSION format:
  • Stage one (Abstraction Submission), a title, abstract, and a list of all co-authors must be submitted by November 29th - CLOSED
  • Stage two (Manuscript Submission), the paper itself is submitted by December 5th- CLOSED

These stages can be done at one time prior to November 29th or if you need more time to complete the manuscript you have the ability to go back into the submission site between November 30th and December 5th and upload the manuscript. 

Authors are responsible for ensuring that their manuscript submission meets all guidelines and that the PDF is readable. To ensure fairness for all submitters, there will be no grace periods to fix a problematic submission.

Authors are responsible for ensuring that their manuscript meets the 2-page paper-length guidelines. There will be no resubmissions to correct this issue.

All EDA manuscript will be reviewed as finished manuscripts.  Preliminary submissions will be at a disadvantage.

Manuscript Submission Rules:
All WACI manuscript submissions MUST adhere to the following rules, and manuscripts that do not adhere to these rules will not be considered for any resubmission.
  1. Submitter must enter the names, affiliations, city, state country and email address of ALL co-authors.
  2. The abstract of approximately 100 words must clearly state the significant contribution, impact, and results of the manuscript
  3. The manuscript must be in PDF format only and be a readable file
  4. The total manuscript file must not exceed two pages (including the abstract, manuscript itself, figures, tables and references)
  5. DO NOT identify the author(s) by their name(s) or affiliation(s) anywhere on the manuscript or abstract, with all references to the author(s)’s own previous work or affiliations in the bibliographic citations being in the third person
  6. Double-columned, 9-pt or 10-pt font
  7. The addition of new co-authors will not be permitted after November 29th
  8. You will not be able to add authors to your manuscript submission if it has been accepted into a DAC session

Review Process:
  • DAC manuscripts go through a double-blind review process; i.e., the identity of authors and reviewers is only known to the TPC co-chairs.
  • DAC ensures that there are no conflicts of interest between authors and reviewers.
  • DAC will compare each submission against a vast database and any manuscript with significant similarity to previously published works or with manuscripts that are simultaneously under review with other venues with archival publications (e.g., conferences, symposia, journals, and workshops with archival proceedings)
  • Duplicate submissions will be rejected. Furthermore, DAC will notify the technical chair of the venue where the duplicate was submitted.

Accept/Rejection Notification:
  • A list of titles of all accepted manuscripts will be posted on the DAC website on February 10, 2012
  • Accept/reject notices will be sent to all authors by email on February 21, 2012, and will be available thereafter to all authors by logging into the DAC website
  • Complete instructions for final manuscript submission and required release forms will be available on the DAC website by March 6, 2012
  • Authors of accepted manuscripts must sign and submit a copyright release form for their manuscript
  • All conference presenters will be required to register at the time of final manuscript

TOPIC AREAS:

Electronic Design Automation (EDA)

SUBMISSION CATEGORIES FOR EDA PAPERS
Authors of research papers are required to specify a category from the list below. Authors of submissions that cover cross-cutting topics (e.g. low-power, reliability, 3-D, etc.) should select a category that is closest to the essential contribution of the submission. Authors may choose a second submission category to accommodate cross-cutting contributions. Please note the separate categories for embedded systems and software topics.

EDA1. System-Level Design & Codesign
EDA1.1 System specification, modeling, simulation, verification, and performance analysis
EDA1.2 Scheduling, HW/SW partitioning, HW/SW interface synthesis
EDA1.3 IP and platform-based design
EDA1.4 Security and IP protection
EDA1.5 Design of Multiprocessor System-On-Chip (MPSOC)
EDA1.6 Application-specific processor design tools

EDA2. System-Level Communication and Networks-on-Chip
EDA2.1 Modeling and performance analysis
EDA2.2 Communications-based design, communication and network synthesis
EDA2.3 Optimization for energy, fault tolerance, reliability
EDA2.4 Interfacing and software issues, beyond-the-die communication
EDA2.5 NoC design methodologies, case studies and prototyping

EDA3. Power Analysis and Low-Power Design
EDA3.1 System-level power design and thermal management
EDA3.2 System/Architectural low-power techniques: partitioning, scheduling, and resource management
EDA3.3 High-level power estimation and optimization
EDA3.4 Gate-level power analysis and optimization
EDA3.5 Device and circuit techniques for low-power design
EDA3.6 Power-aware and energy-efficient wireless protocols, algorithms and design techniques

EDA4. Verification
EDA4.1 Functional, transaction-level, RTL, and gate-level modeling and verification of hardware design
EDA4.2 Dynamic simulation, equivalence checking, formal (and semiformal) verification model and property checking
EDA4.3 Emulation and hardware simulators or accelerator engines
EDA4.4 Modelling languages and related formalisms, verification plan development and implementation
EDA4.5 Assertion-based verification, coverage analysis, constrained random testbench generation

EDA5. High-Level Synthesis, Logic Synthesis, and FPGAs
EDA5.1 Combinational, sequential and asynchronous logic synthesis
EDA5.2 Library mapping, cell-based design and optimization
EDA5.3 Transistor and gate sizing, resynthesis
EDA5.4 Interactions between logic design and layout or physical synthesis
EDA5.5 High-level, behavioral, algorithmic, and architectural synthesis, “C” to gates tools and methods
EDA5.6 Resource scheduling, allocation, and synthesis
EDA5.7 Logic synthesis and physical design techniques for FPGAs
EDA5.8 Configurable and reconfigurable computing

EDA6. Circuit, Interconnect and Manufacturing Simulation and Analysis
EDA6.1 Electrical, thermal, and electro-thermal simulation
EDA6.2 Model order reduction methods
EDA6.3 Interconnect and substrate modeling and extraction
EDA6.4 High-frequency and electromagnetic simulation of circuits
EDA6.5 Process technology characterization, and modeling
EDA6.6 Technology CAD and fab automation

EDA7. Timing Analysis, Integrity and Design Reliability
EDA7.1 Deterministic and statistical timing analysis
EDA7.2 Signal integrity and substrate noise
EDA7.3 Power delivery analysis and optimization
EDA7.4 Electrical and thermal reliability
EDA7.5 Soft errors
EDA7.6 Novel clocking methodologies

EDA8. Physical Design
EDA8.1 Floorplanning, partitioning, placement
EDA8.2 Buffer insertion, routing, interconnect planning
EDA8.3 Physical verification and design rule checking
EDA8.5 Automated synthesis of clock networks
EDA8.6 Physical design of 3-D integrated circuits
EDA8.8 System-in-package design, package-board codesign

EDA9. Design for Manufacturability
EDA9.1 Reticle enhancement, lithography-related design optimizations
EDA9.2 Design for manufacturability, yield, defect tolerance, cost issues, and DFM impact
EDA9.3 Design for resilience under manufacturing variations

EDA10. Analog, Mixed-Signal, and RF
EDA10.1 Analog, mixed-signal, and RF design methodologies
EDA10.2 Automated synthesis
EDA10.3 Analog, mixed-signal, and RF simulation
EDA10.4 High-frequency design and advanced antenna design for wireless design

EDA11. Testing
EDA11.1 Test quality/reliability, current based test, delay test, low-power test
EDA11.2 Digital fault modeling, automatic test generation, fault simulation
EDA11.3 Digital design for test, test data compression, built-in self test
EDA11.4 Memory test and repair, FPGA testing
EDA11.5 Fault-tolerance and online testing
EDA11.6 Analog/mixed-signal/RF testing, system-in-package (SIP) testing
EDA11.7 Board- and system-level test, system-on-chip (SoC) testing
EDA11.8 Silicon debug and diagnosis, post-silicon design validation

EDA12. Design Automation for System & Synthetic Biology
EDA12.1 Design methodologies for system & synthetic biology
EDA12.2 Tools for engineering parts and devices
EDA12.3 Tools for protein and pathway engineering
EDA12.4 Tools for bridging experimental and computational frameworks

EDA13. New and Emerging Design Technologies (including but not restricted to)
EDA13.1 New transistor structures, devices, and novel process technologies
EDA13.2 Nanotechnologies, nanowires, nanotubes
EDA13.3 Optical devices and communication
EDA13.4 Quantum computing
EDA13.5 Biologically-based or biologically-inspired computing systems
EDA13.6 MEMS, sensors, actuators, imaging devices
EDA13.7 Cyber-physical systems

EDA14. EDA Wild and Crazy Ideas (WACI)

 

 

Embedded Systems and Software (ESS)

ESS1. Embedded System Specification and Software Engineering
ESS1.1 Domain-specific programming languages
ESS1.2 Software architectures and software engineering
ESS1.3 Model- and component-based embedded software design
ESS1.4 Software frameworks
ESS1.5 Hardware/software co-specification techniques

ESS2. Embedded Software
ESS2.1 Real-time operating systems and middleware
ESS2.2 Middleware and virtual machines
ESS2.3 OS Runtime support for resources management
ESS2.4 Software techniques for multicore, GPU, multithreaded embedded architectures
ESS2.5 Compilation strategies, code transformation and parallelization techniques for embedded systems
ESS2.6 Static and dynamic timing analysis for embedded systems
ESS2.7 Hardware-dependent software
ESS2.8 Customized interfaces and protocols
ESS2.9 I/O management in embedded systems: device drivers, timers, etc.

ESS3. Architectures for Embedded Systems
ESS3.1 Many- and multi-core embedded architectures
ESS3.2 Application-specific platforms and embedded processors (ASIP) design
ESS3.3. Design of heterogeneous distributed embedded systems including wireless sensor networks
ESS3.4 Run-time and design time reconfigurable platforms and processors
ESS3.5 Architectures for self-adaptive computing systems
ESS3.6 On-chip memory architectures and management: scratchpads, compiler controlled memories, etc.
ESS3.7 Custom storage organizations: flash, etc.
ESS3.8 Custom communication design

ESS4. Embedded System Validation, Verification, Security, Dependability
ESS4.1 Formal verification
ESS4.2 System validation
ESS4.3 Testing and regression analysis
ESS4.4 Hardware/software co-validation
ESS4.5 Hardware and software security and dependability techniques
ESS4.6 Verification techniques for software correctness

ESS5. Embedded Systems Platforms and Case Studies
ESS5.1 Platforms and design flows for domain-specific applications (e.g.,
avionics, automotive, medical, mobile, multimedia, etc.)
ESS5.2 IP-based design
ESS5.3 Rapid prototyping
ESS5.4 Packaging issues
ESS5.5 Case studies

ESS6. Embedded systems design methodologies
ESS6.1 Modeling embedded constraints: performance, reliability, power, security, etc.
ESS6.2 Early estimation and co-simulation of embedded systems designs
ESS6.3 Multiple-constraint-driven embedded system design exploration, synthesis and optimization
ESS6.4 Design methodologies for pervasive distributed networked embedded systems
ESS6.5 Design methodologies for runtime reconfiguration management, self-adaptive systems and autonomous embedded systems
ESS6.6 System level power management and optimization in embedded systems

ESS7. Embedded Systems and Software (ESS) Wild and Crazy Ideas (WACI)


 



Q. What is the DAC WACI manuscript submission timeline?

A. TIMELINE

OCTOBER 2011:
October 11: On line submission opens for WACI abstracts on the DAC website.

NOVEMBER 2011:
November 29: WACI abstract deadline. You will NOT be able to add authors or change the title after this final submission. Double check your abstract and author list prior to submitting!

DECEMBER 2011:
December 5: Final manuscript deadline.

FEBRUARY 2012:
February 20: Accept/reject notifications are sent

MARCH 2012:
March 9: Confirmation form due back to DAC office confirming your acceptance to participate in DAC
March 22: Registration instructions will be sent along with the code necessary for submitting the final manuscript to the Proceedings publisher
March 30: DAC website LIVE with the technical program!

APRIL 2012:
April 4: Final manuscript due to publisher and copyright form due to ACM
April 4: Speaker registration deadline
April 10: Begin to submit your session presentation slides to the Session Chair for review

MAY 2012:
May 7: Presentation slides due for review by the Session Chair
May 21: Speaker bio due
May 21: Session Chair will communicate feedback/reviews of presentation slides
May 30: Final presentation slides due

Q. What Makes a good WACI Manuscript?

A. Break the mold, shift the paradigm, and think outside the box. But do avoid clichés: we are looking for true innovation!
    • A description of a genuinely forward-looking, radical and innovative idea in the area of electronic design or electronic design automation. Controversy is good, incrementalism is bad.
    • A write-up of no more than two pages.
    • A logical exposition of the idea accompanied by insights or back-of-the-envelope calculations that show the promise of the proposed concept.
    • Fewer experimental results than a DAC manuscript – just enough to demonstrate a proof of concept of your idea! If you have complete results, you probably want to submit a research manuscript.

Q. Will WACI authors have to submit a video?

A. WACI accepted authors will be required to submit a short video that highlights the main contributions of the manuscript. The video should be submitted concurrently with the final version of the accepted WACI contribution, and is due with submission of the final manuscript. Please see the DAC website for the 48th DAC WACI videos.

Q. I still have some questions. Who do I contact?

A. For additional information, please contact Soha Hassoun or Donatella Sciuto, 49th DAC Technical Program Co-Chairs.

Q. Do you have a sample of the WACI submission to reference?

Q. Do you have a sample of a WACI Video?

ABSTRACT SUBMISSION:  5:00pm MT,
(-07:00 GMT)
November 29, 2011 - CLOSED

MANUSCRIPT SUBMISSION: DUE BEFORE 5:00pm MT, (-07:00 GMT)
December 5 , 2011- CLOSED


Design Automation Conference Sponsors IEEE Solid State Circuits Society Electronic Design Automation Consortium CEDA - IEEE Council on Electronic Design Automation SIGDA Special Interest Group - Design Automation