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EDA1. System-Level Design & Codesign
EDA1.1 System specification, modeling, simulation, verification, and performance analysis
EDA1.2 Scheduling, HW/SW partitioning, HW/SW interface synthesis
EDA1.3 IP and platform-based design
EDA1.4 Security and IP protection
EDA1.5 Design of Multiprocessor System-On-Chip (MPSOC)
EDA1.6 Application-specific processor design tools
EDA2. System-Level Communication and Networks-on-Chip
EDA2.1 Modeling and performance analysis
EDA2.2 Communications-based design, communication and network synthesis
EDA2.3 Optimization for energy, fault tolerance, reliability
EDA2.4 Interfacing and software issues, beyond-the-die communication
EDA2.5 NoC design methodologies, case studies and prototyping
EDA3. Power Analysis and Low-Power Design
EDA3.1 System-level power design and thermal management
EDA3.2 System/Architectural low-power techniques: partitioning, scheduling, and resource management
EDA3.3 High-level power estimation and optimization
EDA3.4 Gate-level power analysis and optimization
EDA3.5 Device and circuit techniques for low-power design
EDA3.6 Power-aware and energy-efficient wireless protocols, algorithms and design techniques
EDA4. Verification
EDA4.1 Functional, transaction-level, RTL, and gate-level modeling and verification of hardware design
EDA4.2 Dynamic simulation, equivalence checking, formal (and semiformal) verification model and property checking
EDA4.3 Emulation and hardware simulators or accelerator engines
EDA4.4 Modelling languages and related formalisms, verification plan development and implementation
EDA4.5 Assertion-based verification, coverage analysis, constrained random testbench generation
EDA5. High-Level Synthesis, Logic Synthesis, and FPGAs
EDA5.1 Combinational, sequential and asynchronous logic synthesis
EDA5.2 Library mapping, cell-based design and optimization
EDA5.3 Transistor and gate sizing, resynthesis
EDA5.4 Interactions between logic design and layout or physical synthesis
EDA5.5 High-level, behavioral, algorithmic, and architectural synthesis, “C” to gates tools and methods
EDA5.6 Resource scheduling, allocation, and synthesis
EDA5.7 Logic synthesis and physical design techniques for FPGAs
EDA5.8 Configurable and reconfigurable computing
EDA6. Circuit, Interconnect and Manufacturing Simulation and Analysis
EDA6.1 Electrical, thermal, and electro-thermal simulation
EDA6.2 Model order reduction methods
EDA6.3 Interconnect and substrate modeling and extraction
EDA6.4 High-frequency and electromagnetic simulation of circuits
EDA6.5 Process technology characterization, and modeling
EDA6.6 Technology CAD and fab automation
EDA7. Timing Analysis, Integrity and Design Reliability
EDA7.1 Deterministic and statistical timing analysis
EDA7.2 Signal integrity and substrate noise
EDA7.3 Power delivery analysis and optimization
EDA7.4 Electrical and thermal reliability
EDA7.5 Soft errors
EDA7.6 Novel clocking methodologies
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EDA8. Physical Design
EDA8.1 Floorplanning, partitioning, placement
EDA8.2 Buffer insertion, routing, interconnect planning
EDA8.3 Physical verification and design rule checking
EDA8.5 Automated synthesis of clock networks
EDA8.6 Physical design of 3-D integrated circuits
EDA8.8 System-in-package design, package-board codesign
EDA9. Design for Manufacturability
EDA9.1 Reticle enhancement, lithography-related design optimizations
EDA9.2 Design for manufacturability, yield, defect tolerance, cost issues, and DFM impact
EDA9.3 Design for resilience under manufacturing variations
EDA10. Analog, Mixed-Signal, and RF
EDA10.1 Analog, mixed-signal, and RF design methodologies
EDA10.2 Automated synthesis
EDA10.3 Analog, mixed-signal, and RF simulation
EDA10.4 High-frequency design and advanced antenna design for wireless design
EDA11. Testing
EDA11.1 Test quality/reliability, current based test, delay test, low-power test
EDA11.2 Digital fault modeling, automatic test generation, fault simulation
EDA11.3 Digital design for test, test data compression, built-in self test
EDA11.4 Memory test and repair, FPGA testing
EDA11.5 Fault-tolerance and online testing
EDA11.6 Analog/mixed-signal/RF testing, system-in-package (SIP) testing
EDA11.7 Board- and system-level test, system-on-chip (SoC) testing
EDA11.8 Silicon debug and diagnosis, post-silicon design validation
EDA12. Design Automation for System & Synthetic Biology
EDA12.1 Design methodologies for system & synthetic biology
EDA12.2 Tools for engineering parts and devices
EDA12.3 Tools for protein and pathway engineering
EDA12.4 Tools for bridging experimental and computational frameworks
EDA13. New and Emerging Design Technologies (including but not restricted to)
EDA13.1 New transistor structures, devices, and novel process technologies
EDA13.2 Nanotechnologies, nanowires, nanotubes
EDA13.3 Optical devices and communication
EDA13.4 Quantum computing
EDA13.5 Biologically-based or biologically-inspired computing systems
EDA13.6 MEMS, sensors, actuators, imaging devices
EDA13.7 Cyber-physical systems
EDA14. EDA Wild and Crazy Ideas (WACI)
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