Wednesday, June 6
Esplanade Foyer 6:00 - 7:00pm
Despite significant advances in wire length driven placement, the routability of various placement algorithms remains fairly unknown. This is further complicated by the lack of a standard framework and metric(s) to evaluate the routability of a given placement. To further advance the state-of-the-art in placement, we are glad to announce the FIRST DAC CONTEST ON ROUTABILITY-DRIVEN PLACEMENT
Creating easily routable designs is one of the key challenges for modern physical synthesis design closure tools. Numerous factors contribute to making this problem increasingly challenging with advanced process technologies. Increased (re)use of embedded IPs or memories that complicate placement and block wiring channels, non-uniform metal layer stacks designed for higher performance, the pressure to reduce die size to control manufacturing cost, and ever increasingly complex design rules. Consequently, the design closure flow needs to be aware of routability during the entire flow, especially during cell placement.
WINNERS WILL BE ANNOUNCED AT DAC
$2,500 Total Prize
Team Name: Ripple
Team Affiliation: The Chinese Univ. of Hong Kong
Team Members: Xu He, Tao Huang, Wing-Kai Chow, Lam Ka Chun, Evangeline F.Y. Young
Team Name: mPL12
Team Affiliation: UCLA / Beijing Univ.
Team Members: Jason Cong, Guojie Luo, Kalliopi Tsota, Bingjun Xiao
Team Name: SimPLR
Team Affiliation: The Univ. of Michigan
Team Members: Myung-Chul Kim, Jin Hu, Igor Markov
Team Name: NTUplace4
Team Affiliation: National Taiwan Univ.
Team Members: Meng-Kai Hsu, Yao-Wen Chang
Team Name: NCKU-Placer
Team Affiliation: National Cheng Kung Univ.
Team Members: Chung-Lin Lee, Sheng-Wen Chen, Kai-Chung Chan, Jing-Chang Wang
Team Name: VDAPlace
Team Affiliation: National Chiao Tung Univ.
Team Members: Sean Shih-Ying Liu, Ching-Yu Chin, Sheng-De Hu
Team Name: LUCASTE_PDT
Team Affiliation: Politecnico di Torino
Team Members: Luca Sterpone
Team Name: Allecon
Team Affiliation: Tsinghua Univ.
Team Members: Zhongdong Qi, Wenchao Gao, Sifei Wang, Zekun Wu
Team Name: UIPlacer
Team Affiliation: Univ. of Illinois at Urbana-Champaign
Team Members: Haitong Tian, Zigang Xiao
Team Name: Goal
Team Affiliation: Department of Computer Science, National Chiao Tung Univ.
Team Members: Tsung-Han Wu, Shih-Tsang Liao, Ke-Ren Dai
Team Name: NCUplacer
Team Affiliation: Department of Electrical Engineering, National Central Univ.
Team Members: Tai-Chen Chen, Kuo-Ting Liu, Pei-Yu Lee
A new set of advanced benchmarks derived from modern industrial ASIC designs will be released to test the quality of the placement algorithms. These benchmarks can be used to perform both placement and global routing. The academic Bookshelf format for integrated circuit placement will be extended to handle routability-driven
The intent of extending the Bookshelf format is to enable contestants to devise novel techniques to improve the routability of their placements based on realistic estimates of routing congestion.
Contestants will be evaluated on the routability of their placement solutions as determined by a global routing based contest evaluation tool. The contest evaluation tool will be released in advance to all participants. The quality of the solution will be measured on the following metrics:
- Wire length.
- Peak and average global routing congestion.
- Local routing congestion.
Detailed descriptions of the contest evaluation metric as well as evaluation/ranking scheme will be released later along with the contest evaluation tool.
Natarajan Viswanathan, IBM Corp.
Please send all contest-related emails and questions to: email@example.com.