Session 48 | 4:30 pm to 6 pm FAULT SIMULATION AND EXTRACTION OF LOW-LEVEL EFFECTS Chair: Thomas W. Williams - Synopsys, Inc, Boulder, CO Organizers: Kwang-Ting (Tim) Cheng, Irith Pomeranz This session features fault simulation and extraction techniques for digital and analog circuits taking into account low-level effects. The first paper presents fault simulation and test development techniques for analog circuitry. The second paper describes an environment for mixed switch/RTL fault simulation. The third paper introduces a comprehensive fault representation mechanism and a fault simulation procedure for it. The fourth paper presents an efficient extraction method for bridging faults. 48.1 Closing the Gap Between Analog and Digital Testing Khaled Saab, Naim Ben Hamida, Bozena Kaminska - Fluence Technology Inc., Beaverton, OR 48.2 A Switch Level Fault Simulation Environment Venkatram Krishnaswamy, Jeremy Casas, Thomas Tetzlaff - Intel Corp., Hillsboro, OR 48.3S Universal Fault Simulation Using Fault Tuples Kumar Dwarakanath, R.D. (Shawn) Blanton - Carnegie Mellon Univ., Pittsburgh, PA 48.4S An Novel Algorithm to Extract Two-Node Bridges Sujit Thomas Zachariah, Sreejit Chakravarty, Carl D. Roth - Intel Corp., Santa Clara, CA