Session 6 | 2 pm to 4 pm NEW TECHNIQUES FOR SYNTHESIS AND MAPPING Chair: Leon Stok - IBM Corp., Yorktown Heights, NY Organizers: Jason Cong, Malgorzata Marek-Sadowska This session presents progress in synthesis and technology mapping, including combined mapping with gate-decomposition considering area-delay trade-off, BDD-based logic synthesis, fine-grained arithmetic optimization in data path synthesis, XOR-based decomposition, and watermarking of synthesis solutions. 6.1 Area Control and Search Space Limitations for Technology Mapping Dirk-Jan Jongeneel - Delft Univ. of Tech., Delft, The Netherlands Ralph H.J.M. Otten - Delft Univ. of Tech., Delft, The Netherlands Yosinori Watanabe - Cadence European Labs., Roma, Italy Robert K. Brayton - Univ. of California, Berkeley, CA 6.2 BDS: A BDD-Based Logic Optimization System Congguang Yang, Maciej Ciesielski - Univ. of Massachusetts, Amherst, MA Vigyan Singhal - Cadence Berkeley Labs., Berkeley, CA 6.3 A Fine-Grained Arithmetic Optimization for High-Performance/Low-Power Data Path Synthesis Junhyung Um, Taewhan Kim - Korea Advanced Institute of Science, Taejon, Korea C.L. Liu - National Tsing Hua Univ., Hsinchu, Taiwan ROC 6.4S Optimal Low Power XOR Gate Decomposition Hai Zhou - Synopsys, Inc, Mountain View, CA D. F. Wong - Univ. of Texas, Austin, TX 6.5S Watermarking while Preserving the Critical Path Seapahn Meguerdichian, Miodrag Potkonjak - Univ. of California, Los Angeles, CA