TUESDAY KEYNOTE | First Time Right Si but to the Right Specification
Theo Claasen - CTO, Philips Semiconductors,
Eindhoven, The Netherlands
         


 PLENARY PANEL | Embedded System Design in the New Millenium
 Chair: A. Richard Newton, Univ. of California, Berkeley
Panel Members: Tudor Brown - ARM Ltd., Cambridge, UK; Sönke Mehrgardt - Infineon Technologies AG, Munich, Germany; Walden C. Rhines - Mentor Graphics Corp., Wilsonville, OR; Henry Samueli - Broadcom Corp., Irvine, CA; Geoff Tate - Rambus Inc., Mountain View, CA
         ppt files currently unavailable


THURSDAY KEYNOTE | System Design Challenges in the Post-PC Era
Hugo De Man -Senior Research Fellow of IMEC, Professor, Katholieke University, Leuven, Belgium
         


SESSION 5 | Special Session: Life at the End of CMOS Scaling (and Beyond)
5.1 CMOS Transistor Scaling Limit
Chenming Hu
         paper unavailable


5.2 Circuits and Interconnect in Aggressively Scaled MOS
Mark Horowitz
         paper unavailable


5.3 Single Electron Switches and Memory: Devices, Technology and Design Issues
Stephen Y. Chou
     paper and slides unavailable         


SESSION 10 |  Panel - Design Closure: Hope or Hype?
 Panel Members: Raul Camposano, Jacob Greidinger, Patrick Groeneveld, Michael Jackson, Larry Pileggi, Lou Scheffer, Martin Walker
         


SESSION 15 | Panel - EDA Meets .COM: How E-Services Will Change the EDA Business Model
Panel Members: Jacques Benkoski, David Dick, Adriaan Ligtenberg, Mike Schuh, Greg Spirakis, Bruce Toal
         


SESSION 19 | Embedded Compilation Techniques
 19.1 Memory Aware Compilation Through Accurate Timing Extraction
Peter Grun, Nikil Dutt, Alex Nicolau
         


19.2 Compiling Esterel into Sequential Code
Stephen A. Edwards
         

19.3 Interactive Co-Design of High Throughput Embedded Multimedia
Thierry J-F Omnès, Thierry Franzetti, Francky Catthoor
         

19.4 Predicting Performance Potential of Modern DSPs
Naji Ghazal, Richard Newton, Jan Rabaey
         


SESSION 24 |  Designing Systems on a Chip
Session 24.1 is unavailable at the author's request.
24.2 Verification of Configurable Processor Cores
Marinés Puig-Medina, Gülbin Ezer, Pavlos Konas
         


24.3 Design of System-on-a-Chip Test Access Architectures Under Place-and-Route and Power Constraints
Krishnendu Chak
         


 SESSION 29 | Architectures for Embedded Systems
 29.1 System Design of Active Basestations Based on Dynamically Reconfigurable Hardware
Athanassios Boulis, Mani B. Srivastava
         

29.2 Hardware-Software Co-Design of Embedded Reconfigurable Architectures
Yanbing Li, Tim Callahan, Ervan Darnell, Randolph Harr, Uday Kurkure, Jon Stockwood
         

29.3 Communication Architecture Tuners: A Methodology for the Design of High-Performance Communication Architectures for System-on-Chips
Kanishka Lahiri, Anand Raghunathan, Ganesh Lakshminarayana, Sujit Dey
         


SESSION 34 | Reconfigurable Computing Systems
 Session 34.1 is unavailable at the author's request.
34.2 An Architecture-Driven Metric for Simultaneous Placement and Global Routing for FPGAs
Yao-Wen Chang, Yu-Tsang Chang
         


34.3 MorphoSys: Case Study of a Reconfigurable Computing System Targeting Multimedia Applications
Hartej Singh, Guangming Lu, Ming-Hau Lee, Fadi Kurdahi, Nader Bagherzadeh, Eliseu Filho, Rafael Maestre
         


SESSION 39 | Embedded Tutorial: Bridging the Gap Between Full Custom and AISC Design
39.1 Closing the Gap Between ASIC and Custom: An ASIC Perspective
D. G. Chinnery, K. Keutzer
          

39.2 The Role of Custom Design in ASIC Chps
William J. Dally, Andrew Chang
         
39.3 Comments on Bridging the Gap
Udi Kra, Earl Killian, Michael Keating, Martin Lefebvre
         paper unavailable


SESSION 44 | High Performance Microprocessor Design
 44.1 Timing Closure by Design, A High Frequency Microprocessor Design Methodology
S. Posluszny, N. Aoki, D. Boerstler, P. Coulman, S. Dhong, B. Flachs, P. Hofstee, N. Kojima, O. Kwon, K. Lee, D. Meltzer, K. Nowka, J. Park, J. Peter, J. Silberman, O. Takahashi, P. Villarrubia
         


44.2 Multiprocessing Design Verification Methodology for Motorola MPC74XX PowerPC Microprocessor
Jen-Tien Yen, Qichao Richard Yin
         


44.3 A Methodology for Formal Design of Hardware Control with Application to Cache Coherence Protocols
Cindy Eisner, Irit Shitsevalov, Russ Hoover, Wayne Nation, Kyle Nelson, Ken Valk
         


44.4 CGaAs PowerPC FXU
Alan J. Drake, Todd D. Basso, Spencer M. Gold, Keith L. Kraver, Phiroze N. Parakh, Claude R. Gauthier, P. Sean Stetson, Richard B. Brown
         


SESSION 49 | Low Power Design Techniques and Estimation
 49.1 Power Minimization Using Control Generated Clocks
 Srikanth Rao Muroor, S. K. Nandy
         


49.2 Bus Encoding for Low-Power High-Performance Memory Systems
Naehyuck Chang, Kwanho Kim, Jinsung Cho
         


49.3 Run-Time Voltage Hopping for Low-Power Real-Time Systems
Seongsoo Lee, Takayasu Sakurai
         


49.4 Function-Level Power Estimation Methodology for Microprocessors
Gang Qu, Naoyuki Kawabe, Kimiyoshi Usami,
Miodrag Potkonja
         
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