 | New physical synthesis tools have driven a mandatory methodology change moving the design sign-off point up to the RT level, or down into the physical placement domain. Tera Systems' products provide early visibility into design quality, performance, and manufacturability issues with the goal of preventing downstream problems with synthesis and physical design processes. TeraFormŽ drives design convergence and on-time delivery by pinpointing micro-architectural problems and bottlenecks at the RT level, early in the design flow, dramatically accelerating the SoC design cycle.
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| Tera Systems, Inc. is the leader in Hardware Description Language (HDL)-based design planning technology for use by designers of complex System-on-Chip (SoC) semiconductors. The company's products provide early visibility into design quality, performance and manufacturability issues with the goal of preventing downstream problems with synthesis and physical design processes. Using the Tera Systems tools, SoC designers can ensure timing convergence and superior performance before reaching back-end layout or actual silicon where the costs of design errors or changes are extraordinarily high. Tera Systems partners with leading semiconductor vendors to develop highly predictable design methodologies and "golden" tool flows that dramatically accelerate the SoC design cycle. For more information, visit our web site at www.terasystems.com
FREQUENTLY ASKED QUESTIONS
What are Tera Systems origins?
---Our experienced, world-class engineering team comes from leading semiconductor and EDA corporations, including the likes of Avant!, Cadence, Digital Equipment, Intel, Lucent Bell Laboratories, Mentor Graphics, Motorola, Silicon Compiler Systems, Synopsys, and Viewlogic.
What does Tera Systems make?
---Tera Systems, Inc. is the leading EDA vendor of RTL design planning tools and methodology that accelerate time-to-market of deep submicron (DSM) high-performance SoCs.
What is an RTL design planner?
---An RTL design planning system gives logic designers visibility into the impact that their RTL coding decisions have on the quality of silicon produced by downstream implementation tools. An RTL design planner enables meaningful what-if RTL analyses and optimizations while modeling DSM physical effects ? without having to descend to the gate level. The RTL design planner must automatically drive the back-end flow to enable a simpler and more efficient RTL signoff. Careful coupling to synthesis and place-and-route tools assures rapid timing convergence once the design proceeds to a detailed gate-level implementation, without the logic designer having to become a layout expert to achieve a superior silicon implementation. An RTL design planner must include capabilities for full-chip partitioning, optimization, floorplanning, routing, analysis, and visualization. Complex SoC designs must be processed at interactive speeds to enable rapid exploration of alternative micro-architectures and physical implementations. Together, these capabilities should provide logic designers with critical insights at the earliest stages in the design process.
What is TeraFormŽ?
---TeraForm is the EDA industry's leading Register Transfer Level (RTL) design planning system for building deep submicron, high-performance SoCs.
What are the benefits of using TeraForm for SoC design?
---TeraForm:
*Raises abstraction to the RT-Level, providing a scalable SoC design solution and an interactive, multi-million-gate analysis environment.
*Accelerates timing convergence for high-speed deep-submicron integrated circuits by driving back-end tools with hierarchically partitioned modules and design constraints.
*Enables a register-transfer-level (RTL) signoff methodology for dramatically faster design turnaround times.
*Helps designers build performance into their RTL, rather than fine-tuning performance at the gate level.
*Automates hierarchical structured-custom design for improved chip density and performance.
*Integrates with leading gate-level synthesis and place-and-route tools to preserve investments in existing technologies and design flows.
Who will benefit from using TeraForm?
---TeraForm is designed for logic designers who follow an HDL-based top-down design flow and ASIC vendors who wish to implement an RTL signoff methodology.
What operating systems does TeraForm support?
---TeraForm is supported on Windows NT/2000 and Sun Solaris (UNIX).
Does TeraForm handle hierarchical designs?
---TeraForm is fully hierarchical and can handle both top-down and bottom-up design methodologies.
What is the largest design that TeraForm can handle?
---We have tested TeraForm on designs as large as a few million gates and have not found any capacity limitations.
Does TeraForm work with a gate-level netlist?
---TeraForm works well with synthesizable RTL that contains moderate levels of gate instantiations.
Can TeraForm work with legacy designs or hard IP core?
---Within a TeraForm session, legacy designs and hard IP cores are treated as blocks with fixed area, aspect ratio, pinout, and a complex timing model.
Tera Systems, Inc. was founded in 1995, by Tommy Eng, president and Richard Gordon, executive vice president. Our Mission is to provide tools, methodolgies and services that enable front-end SoC designers to make high-impact micro-architecture decisions that improve chip quality, shorten time-to-market and eliminate back-end iterations.
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