44th Design Automation Conference, June 4-8, 2007

 

Mentor Banner May 23

Verification...The final frontier...

Join us for a lunch time voyage on the starship Questa with "Special Guests." Tuesday June 5th, 12:00 - 2:00San Diego Convention Center, Room 29 A/B/C/D Our mission: To explore advanced new technologies...To seek out new tools and new methodologies...To boldly go where no EDA vendor has gone before... Come hear about the Next Generation in Verification Methodology, Solutions and Standards and enter to win an exclusive DAC dinner with guest Star Fleet officers.

Transport for more information and to engage for this event

May 23, 2007

 

Keynote Addresses Anchor DAC Program

Gabe Moretti, Editor

 

Three outstanding speakers will deliver the keynote addresses at this year's Design Automation Conference.  Together, the topics of the addresses will provide a complete look at the future opportunities for both the electronics industry and EDA.  The automobile has taken a central place as a platform for invention and innovation for electronic engineers.  In particular, it can play a major role in spurring development of system-level methods and tools that not only address electronic problems, but also help EDA vendors understand how to integrate EDA tools with others dealing with mechanical, fluid dynamics, and human interface issues.  The semiconductor industry continues to provide more advanced process technologies that present ever-increasing degrees of difficulty for both designers and EDA tools developers. It is a continuing effort to allow engineers to solve problems of increasing complexity in robust and financial sound manners.  Exciting and challenging as these opportunities are, physicists, chemists, and biologists can adapt some of the methods used in EDA to solve new problems in their own fields.  "This year's keynote speakers exemplify the impact of EDA on advancements in so many fields, from semiconductors to automobiles and even biology," said Steve Levitan, general chair of the 44th DAC. "We are delighted to offer our attendees such a distinguished and diverse group of presenters for this year's conference."  The three speeches alone justify your attendance.

 

 

A New Automotive DNA

 

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Dr. Lawrence D. Burns , Vice President of research and Development and Strategic Planning at General Motors Corporation will deliver the first address Monday, June 4, at 2:00 PM.  He oversees GM's advanced technology, innovation programs, and corporate strategy. In addition to driving innovation in today's vehicles, Dr. Burns is championing GM's "reinvention" of the automobile around advanced propulsion, electronics, telematics, and materials technologies.  He began his career in 1969 as a member of the research & development staff, where his research focused on transportation, logistics, and production system.  Dr. Burns subsequently held executive positions in several GM divisions in the areas of product program management, quality, production control, industrial engineering, and product and business planning. In May 1998, he was named a vice president of General Motors, with responsibility for R&D and Planning.

 

Dr. Burns holds a Ph.D. in civil engineering from the University of California at Berkeley. He also has a master's degree in engineering/public policy from the University of Michigan and a bachelor's degree in mechanical engineering from General Motors Institute (now Kettering University).

 

The automotive industry stands on the threshold of a new opportunity stemming from a radical change in the way we approach the problem.  It is similar to creating a new DNA, a new race of vehicles that replaces the internal combustion engine, petroleum, and mechanical linkages with fuel cells and batteries, hydrogen and electricity, and electronic systems and controls.  This new breed of vehicles will revolutionize how a vehicle operates, how we interact with them, and how they communicate with each other and the outside world.  To achieve this, we need to dramatically change how automobiles are designed and built. 

 

EDA is an enabler of innovation and EDA can play a major role in facilitating the birth of new  transportation systems.  

 

Challenges & Solutions for the Semiconductor Industry

 

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Dr. Oh-Hyun Kwon will deliver the second keynote speech during the General Session on Tuesday morning, June 5.  Dr. Oh-Hyun Kwon was appointed president of the System LSI division at Samsung Electronics in 2004. Before joining the System LSI division of Samsung Electronics in 1997, he led the team that developed the industry's first 64M DRAM in 1992 and he was also in charge of various memory technology developments, such as DRAM, SRAM, and flash memory.

 

Dr. Kwon has a Ph.D. in electrical engineering from Stanford University. He received his master's degree in electrical engineering from the Korea Advanced Institute of Science and Technology and a bachelor's degree in electrical engineering from Seoul National University.

 

The huge investment required for new fabrication facilities is forcing many integrated device manufacturers (IDMs) to change their business model to either fablite or fabless.  The significant costs to develop the next generation process technologies demand that various companies join together in consortia in order to financially justify their investments.  Due to severe competition in the consumer markets low chip prices and short time-to-market are both essential.  The reluctance of some system houses to adopt the latest process due to the high development costs associated with such choice increases the complexity of the business problem.  Jim Hogan, Chairman of the Board of Ponte Solutions, has  predicted that at the 45 nm node we will have only five "super fab" consortia and less than a handful of IDMs able to overcome its technological and financial obstacles.  Dr. Kwon will present a perspective on how the semiconductor industry must respond to these challenges by developing new markets, new products, and new technologies.  

 

Design Without Borders

 

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Earlier this year, our industry lost one of its most energetic and insightful leaders: Dr. A. Richard Newton. 

 

Dr. Jan M. Rabaey will present a tribute to Dr. Newton in his speech on Thursday, June 7, at 12:30 PM.  He is the Donald O. Pederson Distinguished Professor in the Department of Electrical Engineering and Computer Sciences at the University of California at Berkeley.  Dr. Rabaey's current research interests include the conception and implementation of next-generation integrated wireless systems.  He has been a visiting professor at the University of Pavia (Italy), Waseda University (Japan), Technical University Delft (Netherlands), Victoria Technical University and the University of New South Wales (Australia). He was the Associate Chair (EE) of the EECS Dept. at Berkeley from 1999 to 2002, and is currently the scientific co-director of the Berkeley Wireless Research Center (BWRC), as well as the director of the GigaScale Systems Research Center (GSRC).  Previously, Dr. Rabaey was a research manager at IMEC, Belgium and prior to that, he was a visiting research engineer the University of California, Berkeley.  Dr. Rabaey received his EE and Ph.D. degrees in applied sciences from the Katholieke Universiteit Leuven, Belgium.

 

Our industry has learned to build highly complex systems by assembling transistors, wires, and passive components into intricate networks.  While its most successful application has been in the area of semiconductor physics, pure engineering has made possible the ability to develop multi-billion transistor chips and to manufacture them in a repetitive, reliable, and cost-effective manner.  We developed a design methodology based on modularization, hierarchy, and abstraction.

 

Today, physicists, chemists, and biologists are exploring components such as molecules, atoms, and enzyme.  Systems built from those components will definitely impact the ways we build mechanical structures, do computing, make drugs, generatee energy and take care of the environment.  Yet, while the nature of the components is drastically different from our silicon devices, the methods for coping with the complexity of the problem remain unchanged.  The art of design developed in the semiconductor industry is just as applicable to these nano- or bio-constructions. 

 

Design methodology is a legacy that will live long after Moore's Law has come to a halt.  To quote Richard, "The future is BDA (Bio Design Automation)".  

Starburst-Register Today

 

 

DAC Quick Links

 

Apache-dac-tile

 

 

Apache delivers the leading power sign-off solutions adopted by top IDM, fabless semiconductor, and foundries, and a complete silicon integrity platform solution for SoC, analog-IP and system designs. Apache’s platform considers all sources of noise that impacts the design, including power, crosstalk, package/system IO, temperature, substrate, and EMI. Apache enables designers to reduce design cost and silicon failure risk. www.apache-da.com.

 

 

Appro International

 

 

HPC & Electronic Simulations Seminar – Limited Seating

June 4th -  11 am - 3 pm at San Diego Convention Center

Please join Appro’s complimentary seminar featuring speakers from IDC, ANSYS, and AMD to learn how High Performance Computing enables companies to deliver leading-edge business results through engineering and electronic simulation technologies.  Register Today!! http://www.appro.com/promotion/seminars/index.html

 

 

Denali Software, Inc.

 

 

Visit Denali at DAC! Booth #6060

Denali experts will be on hand to demonstrate our complete line of Design IP,

Verification IP, Embedded Software, and SystemVerilog solutions, including:

* Design and Verification IP for: PCI Express 2.0 and IOV

* Memory Controller & PHY IP for: DDR1,2,3 and LPDDR DRAM

* HW/SW IP Platform Solution for: MLC NAND Flash

* and complete verification IP for your SystemVerilog migration,

including: AMBA, DDR, Flash, PCIe, PLB, SATA, USB, & more...

Schedule a meeting today: http://www.denali.com/dac2007.html

 

SynCira

SynCira Corp . is excited to show the industries next generation high capacity hierarchical analog circuit layout synthesis technology at DAC in San Diego.  From circuit spice netlist, it generates many GDS layout solutions that achieve 100% constraint satisfaction, near 100% packing density, optimized floorplan, device placement and routing.  SynCira’s technology will slash layout generation time from weeks to hours. Visit our booth #660 or email for more information at info@syncira.com.

 

 

Tanner EDA

 

 

Tanner EDA, the leader in affordable, portable analog/mixed signal IC design tools invites you to Booth 4873. Visit our technical experts for a demonstration of the performance enhancements of T-Spice, our simulation and verification tool. L-Edit, our physical design tool, as well as HiPer, the only hierarchical, foundry-compatible DRC tool on the market. Come join us!