What does DFM Mean for EDA?
Rajeev Madhavan
Chairman and Chief Executive Officer
Magma Design Automation, Inc.
San Jose CA

DFM, does it mean, design for manufacturability or design for marketing? Recently it has been positioned as the next great inflection point in the electronic design automation (EDA) industry that will enable it to expand significantly with an entirely new segment. Just a few months ago as many as 27 different EDA companies offered DFM tools, 21 of which are startups, or so claimed John Cooley on DeepChip.  All of the companies in the DFM market segment are trying to find a foothold and differentiate. In this mad scramble to appear to be first to market with a unique product, hype has gotten way ahead of product delivery. As a result, products that do not meet expectations confuse designers and DFM has come to mean design for marketing. 

As a founder of three companies, and investor and mentor of many others, I can identify with the brilliant engineers who work so hard make these startups successful. When we founded Magma 10 years ago, we had carefully studied emerging deep submicron design challenges. We committed to integrating logic and physical design because we knew that that’s what it would take. We succeeded –– and then some –– but it wasn’t without more challenges than we could have ever anticipated.

I admit that there was a lot of hype around Magma in the early days, but that was for good reason. We were truly changing the way IC design was done so that we could ensure that our customers would achieve their performance, cost and time-to-market requirements. Today, all the large EDA companies claim to have an integrated flow.

There is no doubt that the EDA industry must enable designers to improve the manufacturability and yield of deep submicron designs. With the inherently imperfect IC manufacturing process, slight differences in temperatures, process step durations, chemical concentrations (such as dopant levels) and so forth result in small differences between each wafer, between dies on the same wafer, and between transistors on the same die. As the critical dimensions of structures on the chip have shrunk, small physical variations can result in relatively large electrical variations.

Manufacturing and yield problems typically fall into two main categories: catastrophic or parametric and they originate from systematic or statistical issues. Catastrophic problems are those such as a missing via, which cause the chip to fail completely. By comparison, parametric problems leave the chip functioning, but out of its specified range, such as a 500-MHz device that runs at only 300-MHz or a part that is required to consume less than 5W of power that actually consumes 8W. The origins of both catastrophic and parametric problems can be subdivided into systematic (feature-driven) effects and statistical (random) occurrences. All of which can have a significant impact on area, performance, power consumption and yield.

For most, DFM only means post-processing the GDSII file with a variety of resolution enhancement techniques (RET), such as optical proximity correction (OPC) and phase-shift mask (PSM). This is no longer viable in chips created at the 65-nm technology node and below. To achieve acceptable performance and yield goals, the entire design flow has to become DFM-aware. DFM effects must be taken into account throughout the design flow without lengthening run times and design cycles. Doing that requires tight integration within a highly automated implementation system.

Few companies can offer the necessary integration and automation. The larger EDA companies are following the usual path of acquiring technology in an effort to create an integrated flow. As a result, many of the DFM startups have disappeared and many others are struggling. If the past is any indication of the future, creating an integrated and automated DFM-aware design flow from a disparate set of point tools will be no easy task.