IN THIS ISSUE:

Geoffrey James, Are Analog Designers Secret Luddites?
Ed Sperling, Why is Analog So Difficult?
Viewpoint by Alan Naumann on Multicore Designs
Gabe Moretti, Analog Design and ESL

Larry Burns
Oh-Hyun Kwon
Jan Rabaey

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44th DAC Proceedings

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Multicore designs are driving mainstream designers to quickly adopt new hardware and software design methods. Is your company ready for it?

Alan Naumann
President & CEO
CoWare, Inc.
San Jose, CA

Is your company ready for multicore?
Design automation and software tools suppliers are all on a quest to support the semiconductor and electronic product companies in delivering better multi-processor silicon and products -- faster, more reliably, and at a lower cost. This trend can be seen through the continuous flow of announcements and product releases hitting the market on a daily basis. As the needs around multicore evolve, it appears, however, that simply upgrading existing solutions to support multicore design will not be sufficient for companies to achieve the benefits they expect. Traditional methods for hardware design (RTL), software development (physical prototype boards), and go-to-market strategies (datasheets or “sample silicon”) are breaking down as the number of multicore based designs and types of cores being used increase. Multicore requires companies to re-evaluate methodologies, technologies, and strategies currently in use. Architecture design, software development, and go-to-market strategies are examples of areas that need this re-evaluation.

Many new engineering challenges have resulted from mulitcore platforms. Complex memory hierarchy, intelligent interconnects, heterogeneous processors and cores, and multiple dependent software stacks must be integrated into a system that meets functionality, performance, power, integration, and time-to-market window requirements. Such changes are forcing engineering teams to create tighter connections with their suppliers, and to enable concurrent engineering among the different disciplines involved (hardware, software, system integration, etc). Modeling, simulation, and analysis technologies serving design tasks such as optimization and validation of architectural interconnects and memories, application processor design, hardware/software integration, and system testing must provide a common integrated infrastructure in order to optimize these interactions, as well as each independent aspect of system development.

As development costs associated with multicore designs increase, companies need to focus on making sure that they design and deliver the “right” product for their customers and optimize their own time-to-revenue. This focus requires the ability to capture and validate design requirements more efficiently in the early stage of the design, enable the ecosystem of technology surrounding the design to be available as early as possible, and provide the customer with a solution to accelerate their own development. Datasheets and silicon must be replaced with a continuous process based on simulated hardware models.

In order to achieve their objectives, semiconductor and electronics companies have, over the past several years, experimented with and are starting to deploy electronic system-level (ESL) design methodologies and technologies. These technologies have proven to result in optimized product performance, reduced development cycle time, and overall better customer satisfaction. The development of standards such as SystemC/IEEE1666, TLM, and SPIRIT have created a viable risk mitigation foundation that is now driving a normal technology evolution from proprietary, in-house solutions to standards-based solutions. The technologies have moved from proof-of-concept to a level of maturity that is required for large scale deployment. We are entering the era of ESL 2.0.

Today, we see multicore design challenges as the key driver behind the need to adopt and deploy ESL technologies in production. Discussions now are not about whether to deploy such technologies, but rather how these technologies should be deployed. Multicore is driving ESL, not as a point technology to accelerate specific design tasks, but rather as an infrastructure that directly impacts the overall enterprise’s business operation and capabilities across its internal functions (hardware design, software development, marketing, etc.) and across its supply chain (partners and customers). This is just the beginning. Multicore will drive even more new innovations and new paradigms for electronic product designs that will challenge our traditional design approaches. The world will anoint new winners among the semiconductor- and electronics-intensive product companies. Great opportunities are at the doorstep: Is your company ready to turn on its productivity for multicore designs?

Analog Design and ESL: We Are Not There Yet.

by Gabe Moretti

Two of the three articles in this month's issue deal with analog design challenges.  The third one hails a new season in ESL.

Analog Design.
It is well known that analog issues have become important even in digital design.  So important, in fact, that tools developed to aid engineers to solve this type of problems have seeded a new and growing market segment, DFM.  Companies in this segment are building a bridge that allows designers trained solely in digital design to deal with the physics inherent in all electronic design.

Do we need it?
Geoffrey James' article revisits the issue of analog synthesis and the resistance of the vast majority of analog designers to new tools.   The statement by Ashutosh Mauskar, vice president of product and business development at Magma Design Automation, brought me back to the late 1990s, when digital synthesis was being introduced as a commercial product.

In those days the most prevalent justification by designers for not using the tool was that they could do better than the tool.  And in many cases, but not the majority, that was true.  But the tradeoff was time.  Eventually, acceptance grew, the products matured with greater use, and now synthesis is a natural step in digital design.

Looking back at commercial offerings from companies that pioneered analog synthesis (and went out of business for it), it is easy to see how analog design creation based on parameters manipulation does not solve all of the issues inherent in analog design.  But, as Gary Smith recounts, even this form of analog synthesis may address a significant portion, probably more than 50%, of analog designs, especially when a specific instance of a frequently used analog component is required.

Of course, as the article points out, developers of standard analog parts enjoy high rates of return, so the economic incentive for well-paid designers to adopt new tools or methods is missing.  But how long are we going to continue to integrate discrete analog components in our designs?

I believe that what is needed is a fresh look at analog design methodology.  Let's not try to copy the digital flow.  Just because it worked there does not mean it will work here.  DAC offers the perfect environment to discuss new ideas in analog design methods; I am looking forward to seeing what the dynamics at the 45th DAC in Anaheim will foster.

A lack of consensus
The roundtable hosted by Ed Sperling gives an indication of the economic difficulty of introducing a new tool in a market, the analog design market in this case. One of the issues that has intrigued me for a long time is the question of standards. Should standards precede the development of tools, or should a leading tool be the framework of a standard? I believe that acceptance is not a question of the standard engineering excellence: it is a matter of marketing. It is obvious from the article that people know, at least subconsciously, that an approach to improve efficiency in analog design following the model of digital design automation methods will not work. But it seems apparent that we do not have consensus as to how to begin, let alone proceed with, the work of developing a solution.

The discussion leaves me with the impression that the economic urgency is not yet high enough to fuel the development of a new analog solution. People complain, but do not revolt: in fact, they hardly even demonstrate. Is this a non-problem? Write to me at (gmoretti@gabeoneda.com) and share your opinions.

ESL 2.0
Alan Naumann in his Viewpoint expresses the belief that we have turned the corner in ESL.   The tools, he states, are no longer just an interesting experiment; driven especially by the rapid emergence of heterogeneous multicore systems-on-chip, ESL is now part of accepted development methods.  I think that Alan is correct in identifying a new season in ESL, especially given the complexities of multicore systems design.  But the work is far from over: acceptance of the tools does not mean we have the best methods for system-level design yet.  Much more work is required, mostly in understanding what system-level design really means, and how we can integrate the design of the electronic portion into the total product design.  EDA is a wonderful industry: just when you think you have reached a plateau, you find new mountains loom on the horizon.  DAC, as usual, will provide many venues for designers to explore new heights.

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The DACeZine also has a Letters to the Editor section to allow for shorter contributions to the contents and directions of the publication. When necessary, answers to the letters will come from the appropriate member of the team (including our readers), since I do not (yet) hold the total knowledge of the industry within me. I encourage all of you to write, either a viewpoint or a letter, and state your opinions on matters that impact our industry, the contents of this publication, or, for that matter, the publication itself. Send your letters to: dacezine@dac.com.

I hope you enjoy this DACeZine issue and pass it along to your friends and colleagues: I am sure they will want to subscribe as well. They can do so by visiting the www.dac.com web page.

Thinking Too Small

Are Analog Designers Secret Luddites?

by Geoffrey James

The dream is compelling.  Rather than monkeying around at the Register Transfer Level (RTL), designers will someday work at the Electronic Systems Level (ESL) using a language like SystemC.  The ultimate goal, of course, is to allow designers to create a true System on Chip (SoC) which contains all the circuitry and "software" needed to support an entire product.  Gone will be the busy-work and tweaking that's part and parcel of chip design.  Making SoCs will be simple and easy.

There is only one thing wrong with the dream: it is not going to happen -- at least, not unless something changes when it comes to designing analog and mixed signal.  The sad truth is that after years of attempted automation, designing analog and mixed signal remains a "black art."  And that's becoming even more true as chip manufacturing processes move to 65nm and 45nm.  At the smaller geometries, analog and mixed signal are so difficult that some designers are opting to put the analog on a separate chip.  And that's a trend that (if it becomes truly popular) could keep the ESL/SoC dream forever in dreamland.

However, some industry analysts believe that some of the problem lies not in the difficulty of analog design but in the fact that analog designers are being difficult. "They have always prided themselves in their ability to squeeze that maximum performance out of their design, whether they need to or not," complains former Gartner analyst Gary Smith of GarySmithEDA.com.  As we move to the sub-90nm nodes, it's fair to ask: might the failure to automate analog design be the result, if only in part, of an engineering culture that disdains automation just as Luddites opposed the introduction of machinery in manufacturing?

LITTLE BIG PROBLEMS
There's no question that, from the viewpoint of physics, analog circuitry poses major difficulties at the smaller geometries.  As the component size gets smaller, designs that worked at the larger geometries no longer function predictably.  The physical proximity of circuit elements and the thinness of the "insulation" tend to augment the effects of inductance, capacitance and leakage.  As a result, analog design processes typically involve a great deal of crafting and re-crafting before products can be expected to run correctly, according to Robert B. Pease, NSC's famous analog design guru.

These challenges grow worse as the geometries get smaller, according to Dave Robertson, a product line director at Analog Devices, Inc. in Norwood, MA.  "Designers will have to be prepared for more 'surprises' as the architecture is taken down to the transistor level," he says.  Dave also believes that using ESL to generate SoCs is something of a red herring.  "The future of chip design isn't going to be software coders who back off three notches and handle everything at a high level," he insists , "Electrical engineers will continue to have the primary place in chip design."

The problem is exacerbated by the fact that, when it comes to analog and mixed signal, RTL automation has proven disappointing.  "As much as we wish it weren't the case, the EDA industry really hasn't been able to do that much to help automate the analog design process," mourns Ashutosh Mauskar, vice president of product and business development at Magma Design Automation, "There is simply no practical way that I can currently replace the best analog designers with an EDA tool."

It should be pointed out that the purpose of EDA has never been to replace an engineer with an automated tool.  Instead, the goal is to develop tools that increase the productivity of both digital and analog designers.  The fact that EDA vendors have so far lagged in helping analog designers may be the result of not enough "out of the box thinking".  It may be necessary to explore a new analog design methodology, not just new tools that mirror the methods used in digital design or that attempt to replicate manual analog design processes.

EDA tools don't address analog designs effectively because "every circuit needs to be designed to a level of near perfection," continues Mauskar, "It's like you're a car company but the only kind of car that actually works is a Ferrari.  Something less polished, like a Toyota, simply isn't good enough to get on the road."  Under the circumstances, it's not surprising that the complexity of analog design looks likely to scuttle the dream of a fully automated analog/digital design environment to create SoCs through ESL.  Or so says conventional wisdom.

OVERESTIMATING THE DIFFICULTY
But is conventional wisdom actually correct? Some analysts are beginning to express suspicions that analog designers may be inflating the difficulty involved in creating workable analog circuits.  For one thing, analog designers have been complaining about smaller geometries for so long that their complaints begin to take on an aura of crying wolf, according to Jordan Selburn, principal analyst at the semiconductor market research firm iSuppli. "Ten years ago when I was at Gartner, there was speculation that true SoC would be just a passing trend because there wasn't parity between the digital and analog real estate," he remembers.

Gary Smith points out that analog designers have always been a conservative lot, insisting that their craft was so unique and so special that it essentially trumped the complexity of other aspects of chip design: 

"The first SoC analog crisis came when we moved to 180nm.  DATE was full of papers and presentations on how the 250nm analog section of an SoC would soon take up a majority of the chip area as the digital section of the SoC moved to 180nm and below.  250nm was considered the smallest geometry you could use for analog.  At the next DATE ST introduced 180nm analog circuits.  We are now doing 90nm analog and I've seen some 65nm analog."

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Why Is Analog So Difficult?

EDA vendors and customers square off on what needs to be done to automate analog design flows; custom designs still plague sector

DACeZine sat down with James Lin, VP of the technology infrastructure group at National Semiconductor; Steven Lewis, director of custom IC solutions marketing for analog, RF and mixed signal at Cadence Design Systems; Shrenik Mehta, senior director of frontend technologies and the OpenSPARC program at Sun Microsystems, and the current chairman of the Accellera standards group; and Sandipan Bhanot, president and CEO of Knowlent. What follows are excerpts of that conversation.

by Ed Sperling

Q: There’s a perception across the electronics industry that analog tools aren’t successful. Why not?
Lin: People use the tools, but they don’t meet our expectations. And the tools are not making any progress. There are no major breakthroughs. The Cadence design framework has been there for a long time. They have integrated more tools together and made it more user friendly, but the fundamental theory remains the same. There is no breakthrough technology.
Lewis: The question is whether you can do revolutionary things in analog like you can in the digital world, where you go from 65 nanometers to 45 nanometers to 32 nanometers. Those kinds of breakthroughs don’t happen in the analog world. We have a lot of customers who still make a good living at 0.35 microns, 0.25 microns, and 0.18 microns.
They’re not interested in going further than that because for power and current needs and everything else, those are the right nodes for them to work on.

Q: But some of those customers are now at 0.13 microns, right?
Lewis: Yes, and Virtuoso has the whole gamut. The question is whether there’s something new and revolutionary. People have talked about analog synthesis for a long time, yet that’s never quite jelled. Is it a tool issue, or is it that the technology doesn’t lend itself to synthesis? If you talk to analog folks, even though they have tools for doing optimization or doing statistical analysis, there’s still a thought of, ‘Well, I think my brain is better than the tools would be.’ It takes a long time for us to prove in the tools space that we can do a good job. I don’t see analog tools being revolutionary, but I also don’t see that as a problem. There are always things people wish tools did, but when you do take steps it takes a long time for people to use them. Are the tools driving the analog guys to be better or are the analog guys driving the tools to be better?
Bhanot: I think you need to qualify this. The implementation side changes all the time. There are timing, DFM, and statistical process variation issues. There is also the verification side. If the digital designers did verification the way analog designers do verification, no chip would ever tape out.

Q: Why is that?
Bhanot: That’s one place where revolutionary technology is needed. There are people designing blocks that are purely analog, and people trying to integrate blocks that have analog and digital portions. This mixed signal verification is very different. At the block level, are you doing all the checks that the spec says you should? You’d be surprised at how many companies—even leading-edge companies—don’t do it correctly. There is no easy infrastructure to say it’s done.
Mehta: The real question is whether analog design is an art or a science. On the digital side, having Verilog and VHDL as standards enabled an ecosystem where people could develop around those standards, whether it’s implementation flows or verification flows. That has allowed leading-edge practices to be replicated by a large number of designers. Ten years ago there was formal verification, but it didn’t get practically applied. Standards did help out. With systems on chip, there is a requirement that you put in an analog portion for networking, communication, a lot of the I/Os and the high-speed memory interfaces. You have to improve the analog if you want to get the SoCs out in a timely manner and also have them functional.

Q: What pieces of the analog tools flow work and what pieces don’t?
Bhanot: These standards are good when you’re trying to integrate vertical blocks. You extrapolate up and try to simulate the chip or a big block. But there are no standards for basic analog verification. Everybody is doing their own thing. There is no standard language. That may be part of the reason why test benches and the verification methodology are not portable across simulators, across companies and across flows.
Mehta: That’s an opportunity for a standards organization.
Lin: Having standards is good, but the first things that need to be fixed are the tools. If you look at [digital] synthesis, what became a standard was based on technology from only one company. Because it was successful, other companies adopted their tools to work with it, so they all work very smoothly. We need to fix the tools first. Once the tools are there, that can be the standard.
Bhanot: I agree. The way to drive standards is not by developing a standard first. Whatever people are using becomes the de facto standard.

Q: Standards follow the technology, right?
Lewis: That’s correct. The reason that Verilog and VHDL are successful is that you can standardize the digital flows. They lend themselves to standardization and synthesis. The analog side is custom. It’s either custom analog or custom digital or custom mixed signal. It’s fine tuning and realizing, ‘Oh, that didn’t quite fit,’ or ‘That isn’t exactly where I need it to be.’ You can find that through some standard testing methods, but you can’t create a standard for analog. In theory, SPICE was the standard language for analog, but there is an alphabet of SPICE. They’re not all exactly alike. What it’s coming down to is whether there’s a way to standardize the interface between this custom stuff and the stuff that is standardized. But what the analog guys do best is tinkering, and I don’t know how you standardize tinkering.
Bhanot: That argument works well on the implementation side, where you’re tweaking transistors. But on the verification side, there is a way to standardize. Eventually, when you have silicon, it is going to be put on the same testers to make sure it works. There’s no reason why you can’t bring it up to the SPICE level and the simulator level.

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