NEW this YEAR! DAC gives you another opportunity to become a star.

  1. Video tape yourself asking a compelling question to the DAC DFM Panelists or ESL Panelists. This concept is taken after the Presidential debates. Try to keep your questions to about 30 seconds; excessively long questions are less likely to be selected.
  2. Upload your video to YouTube.
  3. Send the YouTube link (provided on their site when you upload) and your name to randen@mpassociates.com. Let us know to which Panel you are directing your question.

The Chair for the panel will review all the posted videos and choose the best ones to be shown LIVE at DAC during that panel!

TUESDAY June 10, 2008, 4:30 PM - 6:00 PM | 210CD
SESSION 18
PANEL: ESL Hand-off: Fact or EDA Fiction? pdf
Chair: Gary Smith - Gary Smith EDA, Santa Clara, CA
Organizers:
Hiroyuki Yagi - STARC, Yokohama, Japan
Eshel Haritan - CoWare, Inc., San Jose, CA

Moving up in the level of abstraction is the holy grail of EDA. Each transition to the next level of abstraction allows 100x improvement in simulation speed and 100x improvement in design productivity. ESL is being promoted as the next level above RTL, but is it really happening?

- What is exactly ESL? What can be automated?
- Is ESL a new design entry level? What are the benefits of the new entry level?
- Why don’t we see wide adoption by HW designers?
- Did we find another way to gain productivity? Is ESL finally enabling IP reuse?
- Are we going to see a transition from “RTL design/hand-off + Gate level sign-off” to “ESL design/hand-off + RTL sign-off”? What does ESL hand-off mean?
- Can ESL address the design of convergent (multiple) applications?

This panel will discuss if we really need the new ESL tools or current RTL-based tools are sufficient and debate if not ESL then what are the new methodologies/tools/languages required to move to the next level of productivity. Then, it will carry out more in-depth discussions on if the ESL hand-off the next step in design.

- Is there a common formalism/abstraction that captures ESL?
- Is it possible?

Speakers:
Nikil Dutt - Univ. of California, Irvine, CA
Tim Kogel - CoWare, Inc., Aachen, Germany
Giovanni Mancini - The Mathworks, Inc., Natick, MA
Michael McNamara - Cadence Design Systems, Inc., San Jose, CA
Wolfgang Roesner - IBM Corp., Austin, TX
Hidekazu Tangi - Sony Corp., Atsugi, Kanagawa, Japan

 

THURSDAY June 12, 2008, 2:00 PM - 4:00 PM | 210CD
SESSION 48
PANEL: DFM in Practice: Hit or Hype pdf
Chair: Andrew B. Kahng - Univ. of California, San Diego, La Jolla, CA
Organizers:
Juan Rey - Mentor Graphics Corp., San Jose, CA
Nagaraj NS - Texas Instruments, Inc., Dallas, TX

DFM has taken shape by virtue of manufacturers defining a series of “DFM activities”, related to parametric and stochastic yield analysis and recommendations for design changes to improve yield. The picture is made more complex because the view from integrated device manufacturers, pure play foundries, and fabless semiconductor companies is not necessarily the same as they have different needs and constrains. This panel brings together DFM practitioners from each of these communities to discuss real experiences on the adoption level achieved so far as well as the impact in the manufactured products. The panel should be of interest of designers moving to advanced nodes (to learn from the experience of those that have “done it already”) as well as those in the leading edge (such that they can compare experiences).

Speakers:
Rob Aitken - ARM, Sunnyvale, CA
Luigi Capodieci - Advanced Micro Devices, Inc., Sunnyvale, CA
Cliff Hou - Taiwan Semiconductor Manufacturing Company, Hsinchu, Taiwan
Lars Liebmann - IBM Corp., East Fishkill, NY
Riko Radojcic - Qualcomm, Inc., San Diego, CA
Vivek Singh - Intel Corp., Hillsboro, OR