Home DAC Matrix - Tuesday, June 10    
 




















                                                                                            
Ballroom ABC     General Session and Keynote Address 8:30-10:15am
EDA for Digital, Programmable, Multi-radios
Justin R. Rattner, Intel Senior Fellow,
Vice President, Director, Corporate Technology Group and Chief Technology Officer, Intel Corp.
                                                                      
206AB

                    
Session 1
For Designers
iDesign I
                
Session 7
For Designers
SPECIAL SESSION: Student Design Contest
    
Session 13
For Designers
iDesign II
        
207ABC                    
Session 2
SPECIAL SESSION: Enabling Concurrency in EDA
                
Session 8A
PANEL: Reinventing EDA with Manycore Processors
Session 8B
PANEL: Multi-Core SoC Design is the Challenge! What is the Solution?
    
Session 14
Multi-core Simulation, Mixed-signal Power Optimization and Nanodevices
        
208AB

                    
Session 3
CAD for FPGA
                
Session 9
Formal Verification Technology
    
Session 15
Experiences and Advances in Formal and Dynamic Verification
        
209AB
                    
Session 4
Analog Performance Modeling and Synthesis
                
Session 10
Layout Techniques for Modern Chip Designs
    
Session 16
Emerging Nano/Biotechnologies
        
210AB
                    
Session 5
Novel Techniques in Embedded Processor Design
                
Session 11
Application Mapping and Power Efficiency
    
Session 17
Cache Optimization and Embedded Systems Modeling
        
210CD
                    
Session 6
PANEL: Electronics and Politics: What the Industry Needs from the Incoming US Administration
                
Session 12
Variation-aware Design
    
Session 18
For Designers
PANEL: ESL Hand-off: Fact or EDA Fiction?
       
DAC Pav.
Booth #364		                                              
212A                
Workshop
Effective Technical Writing
                                                        
213D                                                
HOTs
Advanced Methodologies in Validating and Integrating High Speed Serial Interconnects in the Ultra Deep Sub-micron CMOS Era
                
204BC    
For Designers
Management Day
        
Booth #2849            
Exhibitor Forum
Morning Sessions followed by 15 minutes of Q & A
                 
Exhibitor Forum
Afternoon Sessions followed by 15 minutes of Q & A
                      
303AB                                
All EDA
IEEE Council on EDA’s Distinguished Speaker Lecture and Lunch		                                      
  Analog/Mixed-signal/RF and Simulation   Business   DFM   Interconnect and Reliability   Low Power Design   New and Emerging Technologies   Physical Design   Strictly Design   Synthesis and FPGA   System-level and Embedded   Verfication and Test   Wireless
Sigda Ph.D. Forum and Member Meeting
6:00 - 7:30pm
Room: 204 Foyer