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- Nanoarch '08
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- Workshop on Hardware-oriented Security and Trust (HOST)
- Gigascale Systems Research Center Quarterly Workshop
- 6th IEEE Symposium on Application Specific Processors
- 7th Symposium on Electronic System-level Design with SystemC
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On-Line Registration has closed for the 45th DAC.
Please check back in April 2009.
How to Register
- Registration Details
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- Scholarship for DAC Alumni between Employment
NEW this YEAR! DAC Speakers are invited to prepare a short video to promote their paper at DAC. The paper previews are available below!
- Jackey Z. Yan - 10.2 DeFer: Deferred Decision Making Enabled Fixed-outline Floorplanner
- Jing Li - 16.2 Modeling of Failure Probability and Statistical Design of Spin-Torque Transfer Magnetic Random Access Memory (STT MRAM) Array for Yield Enhancement
- Vivy Suhendra - 17.3s Exploring Locking & Partitioning for Predictable Shared Caches in Multi-cores
- Sebastian Herbert - 19.1 Characterizing Chip-Multiprocessor Variability-Tolerance
- Liang Yun - 19.2 Cache Modeling in Probabilistic Execution Time Analysis
- Umit Y. Ogras, Radu Marculescu, Diana Marculescu - 35.1 Variation-Adaptive Feedback Control for Networks-on-Chip with Multiple Clock Domains
- Chia-Ming Chang - 40.3 Type-Matching Clock Tree for Zero Skew Clock Gating
Paper: 16.2 Modeling of Failure Probability and Statistical Design of Spin-Torque Transfer Magnetic Random Access Memory (STT MRAM) Array for Yield Enhancement
Paper: 17.3s Exploring Locking & Partitioning for Predictable Shared Caches in Multi-cores
Paper: 35.1 Variation-Adaptive Feedback Control for Networks-on-Chip with Multiple Clock Domains
Paper: 10.2 DeFer: Deferred Decision Making Enabled Fixed-outline Floorplanner
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