| Paper ID |
Manuscript Title |
| 150-AB586 |
Stitch-Aware Routing Framework for Multiple E-Beam Lithography |
| 150-AE668 |
Proactive Circuit Allocation in Multiplane NoCs |
| 150-AG289 |
The Undetectable and Unprovable Hardware Trojan Horse |
| 150-AL186 |
Simulation Knowledge Extraction and Reuse in Constrained Random Processor Verification |
| 150-AO794 |
Optimization of Placement Solutions for Routability |
| 150-AR664 |
Runtime Dependency Analysis for Loop Pipelining in High-Level Synthesis |
| 150-AV327 |
Exploring Tunnel-FET for Ultra Low Power Analog Applications: A Case Study on Operational Transconductance Amplifier |
| 150-AY766 |
Smart Non-Default Routing for Clock Power Reduction |
| 150-BB711 |
Double Patterning Lithography-Aware Analog Placement |
| 150-BG177 |
Minimum-Energy State Guided Physical Design for Nanomagnet Logic |
| 150-BQ272 |
Aging-aware Compiler-directed VLIW Assignment for GPU Architectures |
| 150-BQ854 |
BDS-MAJ: A BDD-based Logic Synthesis Tool Exploiting Majority Logic Decomposition |
| 150-BX63 |
ABCD-L: Approximating Continuous Linear Systems Using Boolean Models |
| 150-CE269 |
Coupling-Aware Length-Ratio-Matching Routing for Capacitor Arrays in Analog Integrated Circuits |
| 150-CO751 |
Ultra Low Power Computing With Resistive Crossbar Nets Using Spin Neurons |
| 150-CP873 |
An Event-Driven Simulation Methodology for Integrated Switching Power Supplies in SystemVerilog |
| 150-CR756 |
Dynamic Voltage and Frequency Scaling for Shared Resources in Multicore Processor Designs |
| 150-CT377 |
Reconciling real-time guarantees and energy efficiency through unlocked-cache prefetching |
| 150-CY467 |
RASTER: Runtime Adaptive Spatial/Temporal Error Resiliency for Embedded Processors |
| 150-DB437 |
Exploiting Just-enough Parallelism when Mapping Streaming Applications in Hard Real-time Systems |
| 150-DC240 |
Workload and User Experience-aware Dynamic Reliability Management in Multicore Processors |
| 150-DF324 |
A Direct Finite Element Solver of Linear Complexity for Large-Scale 3-D Circuit Extraction in Multiple Dielectrics |
| 150-DH639 |
Pareto epsilon-Dominance and Identifiable Solutions for BioCAD Modeling |
| 150-DI264 |
A Counterexample-Guided Interpolant Generation Algorithm for SAT-based Model Checking |
| 150-DV888 |
Towards optimal performance-area trade-off in adders by synthesis of parallel prefix structures |
| 150-EB189 |
Polyhedral Model based Mapping Optimization of Loop Nests for CGRAs |
| 150-ED802 |
An Efficient and Effective Analytical Placer for FPGAs |
| 150-EH488 |
An Efficient Layout Decomposition Approach for Triple Patterning Lithography |
| 150-EL890 |
Constraint Abstraction for Vectorless Power Grid Verification |
| 150-EM894 |
Verification of Digitally-Intensive Analog Circuits via Kernel Ridge Regression and Hybrid Reachability Analysis |
| 150-EN872 |
Efficiently Tolerating Timing Violations in Pipelined Microprocessors |
| 150-ES449 |
Cross-Layer Racetrack Memory Design for Ultra High Density and Low Power Consumption |
| 150-EU418 |
A Method to Abstract RTL IP Blocks into C++ Code and Enable High-Level Synthesis |
| 150-EW445 |
A Novel Fuzzy Matching Model for Lithography Hotspot Detection |
| 150-EX502 |
CoARX: A Coprocessor for ARX-based Cryptographic Algorithms |
| 150-EY760 |
Underpowering NAND Flash: Profits and Perils |
| 150-FC378 |
Enhancing Compiler Techniques for Energy-Efficient Programmable Accelerators |
| 150-FG333 |
Machine-Learning-Based Hotspot Detection Using Topological Classification and Critical Feature Extraction |
| 150-FK148 |
A Layout-based Approach for Multiple Event Transient Analysis |
| 150-FP46 |
Multiple Chip Planning for Chip-Interposer Codesign |
| 150-FX186 |
Peak Power Reduction by Space-time Multiplexing based Demand-supply Matching for 3D Thousand-core Microprocessors |
| 150-GF282 |
Accelerators for Biologically-Inspired Attention and Recognition |
| 150-GP416 |
A Transmission Gate Physical Unclonable Function and On-Chip Voltage-to-Digital Conversion Technique |
| 150-GS330 |
An Optimal Algorithm of Adjustable Delay Buffer Insertion for Solving Clock Skew Variation Problem |
| 150-GU416 |
HyDrA: Architectural Synthesis for Heterogeneous Dark Silicon Chip Multi-processors" |
| 150-GW183 |
Energy-Optimal SRAM Supply Voltage Scheduling under Lifetime and Error Constraints |
| 150-GW623 |
TEASE: A Systematic Analysis Framework for Early Evaluation of FinFET-based Advanced Technology Nodes |
| 150-HF541 |
Compiler-based Side Channel Vulnerability Analysis and Optimized Countermeasures Application |
| 150-HH688 |
Stochastic Circuits for Real-Time Image-Processing Applications |
| 150-HK894 |
XDRA: Exploration and Optimization of Last-level Cache for Energy Reduction in DDR DRAMs |
| 150-HL435 |
NumChecker: Detecting Kernel Control-flow Modifying Rootkits by Using Hardware Performance Counters |
| 150-HO234 |
A Robust Constraint Solving Framework for Multiple Constraint Sets in Constrained Random Verification |
| 150-HP845 |
An Accurate Semi-Analytical Framework for Full-Chip TSV-induced Stress Modeling |
| 150-HQ84 |
LEQA: Latency Estimation for a Quantum Algorithm Mapped to a Quantum Circuit Fabric |
| 150-HV981 |
High-Performance Hardware Monitors to Protect Network Processors from Data Plane Attacks |
| 150-IC65 |
Analysis and Characterization of Inherent Application Resilience for Approximate Computing |
| 150-IR983 |
High-Throughput TSV Testing and Characterization Using Thermal Mapping |
| 150-IS929 |
Post-Placement Voltage Island Generation for Timing-Speculative Circuits |
| 150-IT185 |
An Optimized Page Translation for Mobile Virtualization |
| 150-JH691 |
Improving the Energy Efficiency of Hardware-Assisted Watchpoint Systems |
| 150-JR991 |
Multidimensional Analog Test Metrics Estimation Using Extreme Value Theory and Statistical Blockade |
| 150-JT912 |
Smart Hill Climbing for Agile Dynamic Mapping in Many-Core Systems |
| 150-KI937 |
Energy Optimization by Exploiting Execution Slacks in Streaming Applications on Multiprocessor Systems |
| 150-KJ691 |
Efficient Moment Estimation with Extremely Small Sample Size via Bayesian Inference for Analog/Mixed-Signal Validation |
| 150-KJ711 |
Early Exploration for Platform Architecture Instantiation with Multi-mode Application Partitioning |
| 150-KP149 |
APPLE: Adaptive Performance-Predictable Low-Energy Caches for Reliable Hybrid Voltage Operation |
| 150-KR552 |
A high-level synthesis flow for Iterative Stencil Loop algorithms |
| 150-KS820 |
Exploiting Program-Level Masking and Error Propagation for Constrained Reliability Optimization |
| 150-KZ545 |
Bayesian Model Fusion: Large-Scale Performance Modeling of Analog and Mixed-Signal Circuits by Reusing Early-Stage Data |
| 150-LE437 |
Optimizations for Configuring and Mapping Software Pipelines in Many Core Systems |
| 150-LL237 |
Integrated Instruction Cache Analysis and Locking in Multitasking Real-time Systems |
| 150-LN903 |
An Energy-Efficient Application-Aware Heterogeneous Network-On-Chip Design |
| 150-LO880 |
On Robust Task-Accurate Performance Estimation |
| 150-LR424 |
Handling Design and Implementation Optimizations in Equivalence Checking for Behavioral Synthesis |
| 150-LS106 |
Improving PUF Security with Regression-based Distriller |
| 150-LW673 |
Automatic Design Rule Correction in Presence of Multiple Grids and Track Patterns |
| 150-LZ197 |
On Learning-Based Methods for Design-Space Exploration with High-Level Synthesis |
| 150-MG82 |
Temperature Aware Thread Block Scheduling in GPGPUs |
| 150-MG972 |
Automatic Clustering of Wafer Spatial Signatures |
| 150-MH650 |
Spacer-Is-Dielectric-Compliant Detailed Routing for Self-Aligned Double Patterning Lithography |
| 150-ML116 |
Simultaneous Analog Placement and Routing with Current Flow and Current Density Considerations |
| 150-MN174 |
An ATE Assisted DFD Technique for Volume Diagnosis of Scan Chains |
| 150-MT395 |
Digital-Assisted Noise Eliminating Training for Memristor Crossbar-based Analog Neuromorphic Computing Engine |
| 150-MU558 |
Designing Energy-efficient NoC for Real-time Embedded Systems Through Slack Optimization |
| 150-MY969 |
Techniques for Energy-Efficient Power Budgeting in Data Centers |
| 150-NB487 |
Real-Time Use-Aware Adaptive MIMO RF Receiver Systems for Energy Efficiency Under BER Constraints |
| 150-NF503 |
Lighting the Dark Silicon on Future Processors: A Comprehensive Evaluation of New Design Dimensions |
| 150-NH583 |
A Novel Analytical Method for Worst Case Response Time Estimation of Distributed Embedded Systems |
| 150-NK248 |
netShip: A Networked Virtual Platform for Large-Scale Heterogeneous Distributed Embedded System |
| 150-NL713 |
New ERA: New Efficient Reliability-Aware Wear Leveling for Endurance Enhancement of Flash Storage Devices |
| 150-NM850 |
Adaptive Paired Page Pre-Backup Scheme for MLC NAND Flash Memory |
| 150-NT14 |
On Effective and Efficient In-Field TSV Repair for Stacked 3D ICs |
| 150-NX460 |
Optimization of Quantum Circuits for Interaction Distance in Linear Nearest Neighbor Architectures |
| 150-NY306 |
GPU-Based N-Detect Transition Fault ATPG |
| 150-OD153 |
Speeding up Computation of the max/min of a set of Gaussians for Statistical Timing Analysis and Optimization |
| 150-OD33 |
Verifying SystemC using an Intermediate Verification Language and Symbolic Simulation |
| 150-OM850 |
Early Partial Evaluation in a JIT-compiled, Retargetable Instruction Set Simulator Generated from a High-Level Architecture Description |
| 150-OX134 |
Scalable Vectorless Power Grid Current Integrity Verification |
| 150-PN406 |
Modular System-Level Architecture for Concurrent Cell Balancing |
| 150-PO770 |
SAW: System-Assisted Wear Leveling on the Write Endurance of NAND Flash Devices |
| 150-QE902 |
A Field-Programmable Pin-Constrained Digital Microfluidic Biochip |
| 150-QG369 |
Design of Cyberphysical Digital-Microfluidic Biochips under Completion-Time Uncertainties in Fluidic Operations |
| 150-QJ735 |
Time-Domain Segmentation based Massively Parallel Simulation for ADCs |
| 150-QQ971 |
Precise Timing Analysis for Direct-Mapped Caches |
| 150-RC911 |
Practically Estimate Routing Congestion under Industrial Design Constraints |
| 150-RE859 |
E-BLOW: E-Beam Lithography Overlapping aware Stencil Planning for MCC System |
| 150-RM105 |
The Impact of Electromigration in Copper Interconnects on Power Grid Integrity |
| 150-RM958 |
Path to a TeraByte of On-Chip Memory for PetaByte per Second Bandwidth with milliWatt of Power |
| 150-RV177 |
Simultaneous multithreading support in embedded distributed memory MPSoCs |
| 150-SF916 |
On the Potential of 3D Integration of Inductive DC-DC Converter for High-Performance Power Delivery |
| 150-SH349 |
Liveness Evaluation of a Cyclo-Static DataFlow Graph |
| 150-SK130 |
DuraCache: A Durable SSD Cache using MLC NAND Flash |
| 150-SM516 |
RESP: A Robust Physical Unclonable Function Retrofitted into Embedded SRAM Array |
| 150-SP377 |
Hierarchical Decoding of Double Error Correcting Codes for High Speed Reliable Memories |
| 150-SQ507 |
A New Time-Stepping Method for Circuit Simulation |
| 150-SU315 |
A Scenario-based Run-time Task Mapping Algorithm for MPSoCs |
| 150-SU858 |
Hierarchical Power Management for Asymmetric MultiCore in Dark Silicon Era |
| 150-SZ727 |
VAWOM: Temperature and Process Variation Aware WearOut Management in 3D Multicore Architectures |
| 150-TD625 |
Memory Partitioning for Multidimensional Arrays in High-level Synthesis |
| 150-TI180 |
Post-silicon Conformance Checking with Virtual Prototypes |
| 150-TJ732 |
Gene Modification Identification under Flux Capacity Uncertainty |
| 150-TL774 |
Performance Enhancement of Garbage Collection for Flash Storage Devices: An Efficient Victim Block Selection Design |
| 150-TS753 |
On Testing Timing-Speculatative Circuits |
| 150-TX248 |
Storage Aware Scheduling for Energy Harvesting Embedded System |
| 150-UG33 |
Defect Tolerance in Nanodevice-Based Programmable Interconnects: Utilization Beyound Avoidance |
| 150-UM877 |
Hardware-Efficient On-Chip Generation of Time-Extensive Constrained-Random Sequences for In-System Validation |
| 150-UO425 |
SSDM: A Smart Stack Data Management for Scratchpad based Multi-core Processors (SMPs) |
| 150-UP748 |
Let's put the Car in your Phone! |
| 150-VG517 |
Towards Variation-Aware System-Level Power Estimation of DRAMs: An Empirical Approach |
| 150-VH190 |
TinySPICE: A Parallel SPICE Simulator on GPU for Massively Repeated Small Circuit Simulations |
| 150-VM459 |
Role of Power Grid in Side Channel Attack and Power-Grid-Aware Secure Design |
| 150-VQ331 |
VeriTrust: Verification for Hardware Trust |
| 150-VY584 |
Routability-Driven Placement for Hierarchical Mixed-Size Circuit Designs |
| 150-WA765 |
Distributed Stable States for Process Networks - Algorithm, Analysis, and Experiments on the Intel SCC |
| 150-WE946 |
Pushing the Energy-Efficiency Limits of Inexact DSP Circuits through Reciprocative Error Compensation |
| 150-WF47 |
RalexBorder: An Efficient Isolation Strategy for Network-on-Chip Supporting Server Consolidation |
| 150-WL455 |
High Quality Routability-Driven Placement via Global Router Integration |
| 150-WU348 |
Stochastic Response-Time Guarantee for Non-Premptive, Fixed-Priority Scheduling Under Errors |
| 150-WY134 |
InTimeFix: A Low-Cost and Scalable Technique for In-Situ Timing Error Masking in Logic Circuits |
| 150-WZ570 |
Reliable On-Chip Systems in the Nano-Era: Lessons Learnt and Future Trends |
| 150-XA117 |
Can CAD Cure Cancer? |
| 150-XN786 |
Throughput-Oriented Kernel Porting onto FPGAs |
| 150-XW273 |
Mapping on Multi/Many-core Systems: Survey of Current and Emerging Trends |
| 150-XZ915 |
Low-Power Area-Efficient Large-Scale IP Lookup Engine Based on Binary-Weighted Clustered Networks |
| 150-YC118 |
Rapid Exploration of Processing and Design Guidelines to Overcome Carbon Nanotube Variations |
| 150-YH926 |
Power Benefit Study for Ultra-High Density Transistor-Level Monolithic 3D ICs |
| 150-YM311 |
Retiming for energy-efficient recovery based design |
| 150-YT600 |
Distributed run-time resource management for malleable applications on many-core platfroms |
| 150-YX139 |
Reconfigurable Pipelined Coprocessor for Multi-mode Communication Transmission |
| 150-YX969 |
HCI Tolerant NoC Router Micro-architecture |
| 150-YZ573 |
DMR3D: Dynamic Memory Relocation in 3D Multicore Systems |
| 150-ZD361 |
Quantitative Evaluation of Error Injection Techniques for Robust System Design |
| 150-ZI799 |
Exploration of Upgradeable Models for Physical Model Emulation |
| 150-ZP438 |
Full-Chip Multiple TSV-to-TSV Coupling Extraction and Optimization in 3D ICs |
| 150-ZU340 |
Synthesis of Feedback Decoders for Initialized Encoders |
| 150-ZW879 |
Creation of ESL Power Models for Communication Architectures using Automatic Calibration |
| 150-ZW944 |
Understanding the Trade-offs in Multi-Level Cell ReRAM Memory Design |
| 150-ZX235 |
Taming the Complexity of Coordinated Place and Route |