Topics range from challenges faced by engineers now to those looming on the horizon
LOUISVILLE, CO. –– May 28, 2010 –– The 47th Design Automation Conference (DAC), the premier conference devoted to electronic design and design automation, is pleased to present a program of nine Technical Panels designed to appeal to both electronic design automation (EDA) developers and the design community. The technical panel program focuses on providing attendees with information on tools, methodologies, and best practices for current and future designs. From Tuesday, June 15th, through Thursday, June 17th, panels will range from the first-ever joint User Track/ Technical Panel session, in which designers and design engineering managers describe challenges faced and overcome “in the trenches,” to sessions that address future challenges in EDA, cloud computing and the electronic vehicle. DAC will be held at the Anaheim Convention Center, in Anaheim, CA, from June 13th - 18th, 2010.
DAC technical panels include:
- EDA Challenges and Options: Investing for the Future – With the “great recession” still fresh in our minds, representatives of major EDA stakeholders, including EDAC, SEMATECH, the CEDA Design Technology Council, and academia, come together to forecast the direction in which EDA industry is headed, in the face of unprecedented technological, economic and business challenges.
- Bridging Pre-silicon Verification and Post-silicon Validation – Experts from industry, academia, and EDA will examine the differences and similarities between the pre-silicon and post-silicon worlds, and explore how the gaps between the two can be bridged.
- Who Solves the Variability Problem? – With variability increasing on all fronts, this panel will bring diverse views from academia, foundries, and the fabless and IDM communities, to address next-generation solutions to variability. The scope of the panel will go beyond manufacturing and reach into the world of design and architecture solutions.
- 3-D Stacked Die: Now or Future? – Two years ago, the big unceasing question was "Why 3-D?" Today, as we move forward with the concrete implementation of the technology, the questions that are asked now are "When 3-D?" and "How 3-D?" This panel brings together key thought leaders to tell us how they see 3-D integrated circuits shaping up in the coming year(s), and to outline future challenges associated with 3D technologies in practical design.
- Does IC Design Have a Future in the Clouds? – Cloud computing is all the rage, but precisely what does that mean for the EDA industry? Panelists from inside and outside the industry will discuss the real and perceived hurdles that currently prevent a broad adoption of cloud computing in IC design, and how the industry may overcome those hurdles.
- What’s Cool for the Future of Ultra Low Power Designs? – An international panel of experts will discuss design methodology challenges in the next generation of ultra-low-power and energy-efficient IC designs, covering EDA roadmapping, low-power standards, and design and verification flows.
- Designing the Always-connected Car of the Future – In this educational panel, automotive industry experts discuss the challenges being addressed by OEMs, key suppliers, academia, and tool providers to enable turning the always-connected car into reality.
- Joint User Track/ Panel Session: What Will Make Your Next Design Experience a Much Better One? – A panel of top designers and design engineering managers describe down-to-earth challenges that designers face, and bring their experiences to reflect upon the important question: What needs to change in the design flows and design tools to improve time-to-market and design quality?
- What Input Language Is the Best Choice for High-level Synthesis (HLS)? – As of 2010, over 30 of the world’s top semiconductor/systems companies have adopted HLS, but what have they learned? Advocates of ANSI-C/C++, SystemC, and BSV compare choices to answer the question, “What input-language works best?”
The full technical program schedule, including panel descriptions, can be viewed at www.dac.com.
“The DAC technical panels this year have unprecedented outreach to the end-user. Attendees will gain practical information on best practices for today, as well as preparation for future challenges,” said Greg Spirakis, Consultant and DAC Panels Chair. “We are grateful to the luminaries from across the industry, including design managers, R&D and design engineers, and academics, who are serving on panels and who are contributing to such a strong program.”
About DAC
The Design Automation Conference (DAC) is recognized as the premier event for the design of electronic circuits and systems, and for Electronic Design Automation (EDA) and silicon solutions. A diverse worldwide community representing more than 1,000 organizations attends each year, represented by system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities. Close to 60 technical sessions selected by a committee of electronic design experts offer information on recent developments and trends, management practices and new products, methodologies and technologies. A highlight of DAC is its Exhibition and Suite area with approximately 200 of the leading and emerging EDA, silicon, IP and design services providers. The conference is sponsored by the Association of Computing
Machinery/Special Interest Group on Design Automation (ACM/SIGDA), the Electronic Design Automation Consortium (EDA Consortium), and the IEEE Council on Electronic Design Automation (CEDA).
Design Automation Conference acknowledges trademarks or registered trademarks of other organizations for their respective products and services.
For more information, please contact: Press@dac.com
Michelle Clancy
303-530-4333