LOUISVILLE, Colo. –– May 4, 2012 – Industry luminaries from ARM, Inc., IBM Corp., Intel Corp. and the National Tsing Hua University will give the three keynote addresses at the 49th Design Automation Conference (DAC), the premier conference devoted to design and design automation of electronic systems. DAC 2012 will be held at the Moscone Center in San Francisco, California, from June 3-7, 2012.
“In assembling the 49th DAC series of distinguished keynotes speakers, I am excited to announce that DAC is covering all bases, providing refreshing viewpoints for systems designers, IC designers and EDA software professionals,” said Patrick Groeneveld, General Chair of the 49th DAC. “Tuesday kicks off with ARM’s Mike Muller, who will share his vision for a future of embedded computing systems. Given that ARM’s processors power most smartphones, this will show the way for computing in the future. On Wednesday, Joshua Friedrich and Brad Heaney will outline the design practices for high-performance microprocessors. This unique dual-keynote provides a look in the kitchen of leading microprocessor companies designing the world’s most advanced chips,” Patrick enthusiastically continued. “Finally, the Thursday keynote by Kaufman Award winner Dave Liu addresses the algorithmic revolution behind EDA. Prof. Liu’s contributions and insights have enabled the remarkable design automation revolution that actually powers today’s trillion-transistor devices.”
All keynotes will be held in rooms 102/103.
Tuesday, June 5, 2012 from 8.30am to 9.30am
Comparing the original ARM design of 1985 to those of today’s latest microprocessors, Mike will look at how far has design come and what EDA has contributed to enabling these advances in systems, hardware, operating systems, and applications as well as how business models have evolved over 25 years. He will then speculate on the needs for scaling designs into solutions for 2020 from tiny embedded sensors through to cloud-based servers that together enable the “Internet of things.” Mike will look at the major challenges that need to be addressed to design and manufacture these systems and propose some solutions.
Wednesday, June 6, 2012 from 10.45am to 11.45am
- Designing High Performance Systems-on-Chip
- Joint presentation by:
- Joshua Friedrich, Senior Technical Staff Member and Senior Manager of POWERTM Technology Development in IBM’s Server and Technology Group.
- Brad Heaney, Intel Architecture Group Project Manager, Intel Corp., Folsom, CA.
Experience state-of-the art design through the eyes of these two experts. Joshua Friedrich will talk about POWER processor design and methodology directions and Brad Heaney will discuss designing the latest Intel architecture multi-CPU and GPU. In this unique dual-keynote, the speakers will cover key challenges, engineering decisions and design methodologies to achieve top performance and turn-around time. The presentations describe where EDA meets practice under the most advanced nodes.
Thursday, June 7, 2012 from 11:00am to 12:00pm
Dave tells us: “It was June 1982 that I had my first technical paper in the EDA area presented at the 19th Design Automation Conference. It was exactly 20 years after I completed my doctoral study and exactly 30 years ago from today. I would like to share with the audience how my prior educational experience prepared me to enter the EDA field and how my EDA experience prepared me for the other aspects of my professional life.”
About the Speakers
Mike Muller was one of the founders of ARM, which provides the embedded processor in nearly every mobile device. Before joining the company, he was responsible for hardware strategy and the development of portable products at Acorn Computers and was part of the original ARM design team. He was previously at Orbis Computers , which developed network computers. At ARM, he was VP Marketing from 1992 to 1996 and EVP, Business Development until October 2000, when he was appointed Chief Technology Officer. In October 2001, he was appointed to the board of ARM Holdings plc.
Joshua Friedrich is a Senior Technical Staff Member and Senior Manager of POWERTM Technology Development in IBM’s Server and Technology Group. In his role, Josh leads the physical design, technology direction, and methodology of IBM’s future POWERTM processors. Josh has been part of the POWER development team since POWER4TM. In addition to POWERTM designs, Josh has led multiple design disciplines, including power estimation and reduction, hardware characterization, memory subsystem circuit development, and core execution units. Before joining IBM, Josh received his Bachelor of Science in Electrical Engineering from the University of Texas at Austin.
Brad Heaney is an Intel Architecture Group Project Manager and operates out of Intel’s Folsom Design Center. Brad is a 25-year veteran at Intel and started his career working on the design of the 80386 family of CPUs. He is the holder of four patents for his design work. In the last few years, Brad has been managing the teams that deliver Intel’s lead vehicles for ramping new process technologies. Brad’s team developed the Penryn CPU, which was a lead vehicle for 45nm process technology. In April of this year, they launched the Ivybridge CPU (3rd-generation Intel Core Processor), which is the lead vehicle for Intel’s 22nm process technology. Brad received his Bachelor of Science degree from Drexel University in Philadelphia and his Master of Science in Electrical Engineering degree from Stanford University prior to joining Intel.
C. L. (David) Liu
C. L. Liu received his B.Sc. degree (1956) from the National Cheng Kung University in Taiwan, and his S.M. (1960) and Sc.D. (1962) degrees from the Massachusetts Institute of Technology. He taught at the Massachusetts Institute of Technology, the University of Illinois at Urbana-Champaign, and the National Tsing Hua University in Taiwan. He also served as the President of the National Tsing Hua University from 1998 to 2002.
C. L. is currently the William Mong Honorary Chair Professor of Computer Science at the National Tsing Hua University, an industrial consultant, and the host of a weekly radio show (since 2005). He has published over 180 technical papers; eight technical textbooks and research monographs in the area of EDA, computer-aided instruction, real-time systems, combinatorial optimization, and discrete mathematics; and seven essay collections in the area of science and humanities.
The Design Automation Conference (DAC) is recognized as the premier event for the design of electronic circuits and systems, and for electronic design automation (EDA) and silicon solutions. A diverse worldwide community representing more than 1,000 organizations attends each year, represented by system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities. No less than 60 technical sessions selected by a committee of electronic design experts offer information on recent developments and trends, management practices and new products, methodologies and technologies. A highlight of DAC is its exhibition and suite area with over 200 of the leading and emerging EDA, silicon, intellectual property (IP) and design services providers. The conference is sponsored by the Association for Computing Machinery (ACM), the Electronic Design Automation Consortium (EDA Consortium), and the Institute of Electrical and Electronics Engineers (IEEE), and is supported by ACM's Special Interest Group on Design
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