Home / DAC 2013 / Call for Contributions / "Wild and Crazy Ideas" WACI

"Wild and Crazy Ideas" WACI

The WACI sessions feature novel (and even preliminary or unproven) technical ideas.

DAC invites submissions with genuinely forward-looking, radical, and innovative ideas in the area of electronic design or electronic design automation.

The aim of WACI is to promote revolutionary and way-out ideas that do not fit the conventional mold, that inspire discussion among conference attendees, that create a buzz, and that get people talking. Research that incrementally improves on prior work is not suited for this category.

WACI submissions may present less-developed, but highly innovative ideas related to areas relevant to DAC. They do not have to explore specific technology problems/solutions with extensive experimental results (as with regular DAC manuscript submissions).

All WACI accepted manuscripts will be required to post a two-minute video describing the work as part of the acceptance process. See 2012 WACI videos

SUBMISSION FORMAT

Stage one (Abstract Submission), a title, abstract, and a list of all co-authors must be submitted by November 27. You may also submit the manuscript at this time if ready
Stage two (Manuscript Submission), the paper itself is submitted by December 3

Authors are responsible for ensuring that their manuscript meets the following guidelines. There will be no resubmissions to correct any issues.

All EDA manuscript will be reviewed as finished manuscripts. Preliminary submissions will be at a disadvantage.

SUBMISSION RULES (Abstract & Manuscript)

The abstract of approximately 100 words must clearly state the significant contribution, impact, and results of the manuscript
The manuscript must be in PDF format only and be a readable file
The total manuscript file must not exceed two pages (including the abstract, manuscript itself, figures, tables and references)
DO NOT identify the author(s) by their name(s) or affiliation(s) anywhere on the manuscript or abstract, with all references to the author(s)'s own previous work or affiliations in the bibliographic citations being in the third person
Double-columned, 9-pt or 10-pt font
The addition of new co-authors will not be permitted after November 27

REVIEW PROCESS

DAC manuscripts go through a double-blind review process; i.e., the identity of authors and reviewers is only known to the TPC co-chairs.
DAC ensures that there are no conflicts of interest between authors and reviewers.
DAC will compare each submission against a vast database and any manuscript with significant similarity to previously published works or with manuscripts that are simultaneously under review with other venues with archival publications (e.g., conferences, symposia, journals, and workshops with archival proceedings)
Duplicate submissions will be rejected. Furthermore, DAC will notify the technical chair of the venue where the duplicate was submitted.

SUBMISSION CATEGORIES

Electronic Design Automation (EDA)

SUBMISSION CATEGORIES FOR EDA PAPERS
Authors of research papers are required to specify a category from the list below. Authors of submissions that cover cross-cutting topics (e.g. low-power, reliability, 3-D, etc.) should select a category that is closest to the essential contribution of the submission. Authors may choose a second submission category to accommodate cross-cutting contributions. Please note the separate categories for embedded systems and software topics.

EDA1. System-Level Design & Codesign
EDA1.1 System specification, modeling, analysis, simulation, verification, and performance analysis
EDA1.2 Scheduling, HW/SW partitioning, HW/SW interface synthesis
EDA1.3 IP and platform-based design
EDA1.4 Security and IP protection
EDA1.5 Design of Multiprocessor System-On-Chip (MPSOC) and case studies
EDA1.6 Application-specific processor design tools

EDA2. System-Level Communication and Networks-on-Chip
EDA2.1 Modeling and performance analysis
EDA2.2 Communications-based design, communication and network synthesis
EDA2.3 Optimization for energy, fault tolerance, reliability
EDA2.4 Interfacing and software issues, beyond-the-die communication
EDA2.5 NoC design methodologies, case studies and prototyping

EDA3. Power Analysis and Low-Power Design
EDA3.1 System-level power design and thermal management
EDA3.2 System/Architectural low-power techniques: partitioning, scheduling, and resource management
EDA3.3 High-level power estimation and optimization
EDA3.4 Gate-level power analysis and optimization
EDA3.5 Device and circuit techniques for low-power design
EDA3.6 Power-aware and energy-efficient wireless protocols, algorithms and design techniques

EDA4. Verification
EDA4.1 Functional, transaction-level, RTL, and gate-level modeling and verification of hardware design
EDA4.2 Dynamic simulation, equivalence checking, formal (and semiformal) verification model and property checking
EDA4.3 Emulation and hardware simulators or accelerator engines
EDA4.4 Modeling languages and related formalisms, verification plan development and implementation
EDA4.5 Assertion-based verification, coverage analysis, constrained random testbench generation

EDA5. High-Level Synthesis, Logic Synthesis, and FPGAs
EDA5.1 Combinational, sequential and asynchronous logic synthesis
EDA5.2 Library mapping, cell-based design and optimization
EDA5.3 Interactions between logic design and layout or physical synthesis
EDA5.4 High-level, behavioral, algorithmic, and architectural synthesis, "C" to gates tools and methods
EDA5.5 Resource scheduling, allocation, and synthesis
EDA5.6 Logic synthesis and physical design techniques for FPGAs
EDA5.7 Configurable and reconfigurable computing

EDA6. Analog Design and Simulation
EDA6.1 Analog, mixed-signal, and RF design methodologies
EDA6.2 Automated synthesis and optimization of analog designs
EDA6.3 Analog, mixed-signal, and RF simulation
EDA6.4 High-frequency and electromagnetic simulation
EDA6.5 Model order reduction techniques for analog/RF designs
EDA6.6 Substrate noise simulation for analog/RF designs

EDA7. Physical Design and Design Closure
EDA7.1 Floorplanning, partitioning, placement
EDA7.2 Buffer insertion and interconnect planning
EDA7.3 Routing and congestion analysis
EDA7.4 Transistor and gate sizing, local physical synthesis
EDA7.5 Clock network synthesis
EDA7.6 Physical verification and design rule checking
EDA7.7 Physical design of 3-D integrated circuits
EDA7.8 Reticle enhancement, lithography-related design optimizations

EDA8. Analysis of Digital Design
EDA8.1 Deterministic and statistical timing analysis
EDA8.2 Electrical simulation, delay modeling and library characterization
EDA8.3 Electrical and thermal reliability, electrical-thermal simulation
EDA8.4 Power delivery analysis and reduction
EDA8.5 Signal integrity and crosstalk modeling
EDA8.6 Process technology characterization, BEOL extraction, and modeling
EDA8.7 Timing and signal/power integrity analysis of 3-D ICs
EDA8.8 Novel clocking methodologies

EDA9. Test and Reliability
EDA9.1 Test quality/reliability, current based test, delay test, low-power test
EDA9.2 Digital fault modeling, ATPG, DFT, BIST, compression
EDA9.3 Memory / FPGA test and repair
EDA9.4 Fault-tolerance and online testing
EDA9.5 Analog/mixed-signal/RF testing
EDA9.6 Board- and system-level test, system-on-chip (SOC) testing
EDA9.7 Silicon debug and diagnosis, post-silicon design validation
EDA9.8 Soft errors
EDA9.9 Design for resilience under manufacturing variations
EDA9.10 Design for manufacturability, yield, defect tolerance, cost issues, and DFM impact
EDA9.11 Testing of 3-D ICs

EDA10. New and Emerging Design Technologies (including but not restricted to)
EDA10.1 New transistor structures, devices, and novel process technologies
EDA10.2 Nanotechnologies, nanowires, nanotubes
EDA10.3 Optical devices and communication
EDA10.4 Quantum computing
EDA10.5 Biologically-based or biologically-inspired computing systems
EDA10.6 MEMS, sensors, actuators, imaging devices
EDA10.7 Design Automation for System & Synthetic Biology

EDA11. Electronic Design Automation (EDA)Wild and Crazy Ideas (WACI)

Embedded Systems and Software (ESS)

ESS1. Embedded System Specification and Embedded Software
ESS1.1 Embedded systems specification methodologies
ESS1.2 Model- and component-based embedded software design
ESS1.3 Embedded software verification
ESS1.4 Operating systems for embedded systems, middleware and virtual machines
ESS1.5 OS Runtime support for resources management
ESS1.6 Software techniques for multicore, GPU, multithreaded embedded architectures
ESS1.7 Compilation strategies, code transformation and parallelization techniques for embedded systems
ESS1.8 Static and dynamic timing analysis for embedded systems
ESS1.9. Hardware-dependent software
ESS1.10 Customized interfaces and protocols
ESS1.11 I/O management in embedded systems: device drivers, timers, etc.

ESS2. Architectures for Embedded Systems
ESS2.1 Many- and multi-core embedded architectures
ESS2.2 Application-specific platforms and embedded processors (ASIP) design
ESS2.3. Design of heterogeneous distributed embedded systems including wireless sensor networks
ESS2.4 Run-time and design time reconfigurable platforms and processors
ESS2.5 Architectures for self-adaptive computing systems
ESS2.6 On-chip memory architectures and management: scratchpads, compiler controlled memories, etc.
ESS2.7 Custom storage organizations: flash, etc.
ESS2.8 Cyberphysical systems: design, analysis and optimization of networked control and switched control systems, architectures, case studies

ESS3. Embedded System Validation, Verification, Security, Dependability
ESS3.1 Formal verification, validation and testing of embedded systems
ESS3.2 Hardware/software co-validation
ESS3.3 Hardware and software security techniques
ESS3.4 Dependable and safety-critical embedded systems: design and case studies

ESS4. Embedded Systems Design Methodologies
ESS4.1 Modeling embedded constraints: performance, reliability, power, security, etc.
ESS4.2 Early estimation and co-simulation of embedded systems designs
ESS4.3 Multiple-constraint-driven embedded system design exploration, synthesis and optimization
ESS4.4 Design methodologies for pervasive distributed networked embedded systems
ESS4.5 Design methodologies for runtime reconfiguration management, self-adaptive systems and autonomous embedded systems
ESS4.6 System level power management and optimization in embedded systems

ESS5. Embedded Systems and Software (ESS) Wild and Crazy Ideas (WACI)

Q. What is the DAC WACI manuscript submission timeline?

A. TIMELINE:

October 11	Abstract submission site OPENS
November 27	Abstract deadline: 5:00pm MT (-07:00 GMT)
December 3	Final manuscripts deadline: 5:00pm MT (-07:00 GMT)
January 17 - 23	Author clarification
February 4	A list of accepted manuscripts is posted on the website
February 14	Accept/Reject notification
March 18	Speaker registration and Copyright form deadline.
March 28	Final manuscript is DUE to the proceedings publisher by 5:00pm MT (-07:00 GMT).
May 7	Draft speaker presentation slides deadline
May 17	Receive feedback on speaker slides from Session Chair
May 21	Speaker bios are DUE to the DAC Navigation Center
June 2	The Design Automation Conference begins!

Q. What Makes a good WACI manuscript?

A. Break the mold, shift the paradigm, and think outside the box. But do avoid clichés: we are looking for true innovation!

A description of a genuinely forward-looking, radical and innovative idea in the area of electronic design or electronic design automation. Controversy is good, incrementalism is bad.
A write-up of no more than two pages.
A logical exposition of the idea accompanied by insights or back-of-the-envelope calculations that show the promise of the proposed concept.
Fewer experimental results than a DAC manuscript - just enough to demonstrate a proof of concept of your idea! If you have complete results, you probably want to submit a research manuscript.

Q. Will WACI authors have to submit a video?

A. WACI accepted authors will be required to submit a short video that highlights the main contributions of the manuscript. Please see the DAC Archive for WACI video examples. 49th DAC WACI videos.

Q. What is the process for Accept/Reject notification?

A. A list of accepted manuscripts will be posted on the DAC website on February 4, 2013. Reviews can be accessed by logging into the DAC Navigation Center on February 14

Authors of accepted manuscripts must agree to the following:

Submit a final paper for the conference proceedings
Register for the conference prior to March 18, 2013
Attend the conference and present their paper and poster

ACM and IEEE reserve the right to exclude a manuscript from archival distribution after the conference if the manuscript is not presented by one of the co-authors at the conference, or in other exceptional cases. DAC will support the IEEE Prohibited Authors List.

Q. Where can I find samples of previously acceoted WACI submission?

A. Please go to the DAC Archives for previously accepted submissions.

Q. Who do I contact for more information?

A. For additional information, please contact Donatella Sciuto or Chuck Alpert, 50th DAC Technical Program Co-Chairs.

ABSTRACT SUBMISSION:
-CLOSED-
November 27, 2012

MANUSCRIPT SUBMISSION:
-CLOSED-
December 3, 2012

Access your DAC Navigation Center

Suggested ACM Proceedings Templates
You can view previously accepted research manuscripts on the DAC Archive.

IMPORTANT COPYRIGHT FORM INFORMATION:
All papers that are submitted to DAC for publication in the official conference proceedings will be required by ACM to sign a copyright form. A sample copy of the ACM Copyright form can be found here so that authors can get the approval process started with their organizations. This copyright sample is for your information only. Authors will be required to complete an electronic version of this form through the ACM submission system in February if their paper is accepted.

Please note: Paper forms are no longer accepted and ACM will not accept any addenda to this form.

Any issues/questions authors have regarding the copyright form or ACM Policy may be addressed to RightsReview@acm.org.