Displaying results 1-10 (of 25)
Geographically diverse design teams obviously face a number of challenges in the creation and verification of the IPs that form a functioning system-on-chip (SOC). Design teams often grow organically and have local versions of design tools, with the related licensing and operating systems to support these tools, and means to check-in and out those designs with other teams. Design datasets require version control of their source files, and verification sign-off steps must occur at each stage of the design process. Questions naturally arise whether design IP has been verified using the correct application and technology libraries?
[read more]
Karen Chow
/
Jul 19, 2011
For sensitive mixed-signal designs at small process nodes, the influence of parasitic elements is growing with the increasing interactions among devices and interconnects that are in close proximity. Circuits are highly sensitive to these parasitic effects, and accurate parasitic extraction is critical for first silicon success. New 3D parasitic extraction technology applied to a flash ADC circuit design reduces the need for extra guardbanding and ensures that it will work according to the specifications when manufactured.
[read more]
Samta Bansal
/
Jun 2, 2011
As demands accelerate for increasing density, higher bandwidths, and lower power, many IC design teams are looking up – to 3D ICs with through-silicon vias (TSVs). 3D ICs promise “more than Moore” integration by packing a great deal of functionality into small form factors, while improving performance and reducing costs. 3D IC packages may accommodate multiple heterogeneous die -- such as logic, memory, analog, RF, and micro-electrical mechanical systems (MEMS) -- at different process nodes, such as 28nm for high-speed logic and 130nm for analog. This provides an alternative to system-on-chip (SoC) integraton, potentially postponing an expensive move to a new process node for all of the functionality developers want to place in a single package.
[read more]
Dave Desharnais
/
Apr 24, 2011
While Silicon Realization encompasses most of what the industry has defined as traditional “EDA,” it goes far beyond this definition by outlining a deterministic path to silicon that is broader, more efficient, and more effective than today’s point-tool based approaches. In its fullness, Silicon Realization addresses the business and technology challenges of complex silicon development, and enables design, implementation, and verification teams to attain higher levels of productivity, predictability, and profitability.
[read more]
Paul McLellan
/
Jan 26, 2011
This is an overview of the current state of 3D chips, or, in particular what has become known as 2½ D chips based on silicon interposer technology using through-silicon vias (TSVs). It is based on the keynotes at the 3D architectures for semiconductor integration
[read more]
Mark Waller
/
Jan 25, 2011
Design constraints, which express design intent, are one of the pieces of ancillary data that are critical to the success or failure of a custom design. Design constraints aren’t usually contained within layout files or library information, but without these critical data, designs may not meet specifications. Today, most custom design teams manage constraints in ad-hoc, manual fashions. This ad-hoc approach has become a significant limitation when it comes to automating the custom design process, which in turn can limit both design productivity and accuracy. Moving forward, the custom design community is starting to look to standards efforts to ease the burden of correlating and communicating design constraints throughout the design process.
[read more]
Hazem Hegazy
/
Jan 5, 2011
In the past decade, the term "DFM" (design for manufacturing) was a massively used semiconductor industry buzzword. In reality, different people interpreted DFM to have different meanings. Some people thought of resolution enhancement technologies (RET) used in the creation of lithography masks for IC fabrication. Others viewed DFM from the design and physical verification side, which involved techniques such as critical area analysis, critical feature analysis, metal fill, litho hotspot detection, etc.
In recent years, another buzzword was introduced: electrical DFM or "eDFM." Although it includes the general term, DFM, the added "e" makes it a more specific definition referring to the electrical effects of manufacturing variation on parametric yield. For a designer, eDFM makes intuitive sense because it translates complex manufacturing concerns into a meaningful electrical property that he or she can understand and may be able to control. This paper looks at eDFM for digital designs.
[read more]
Joseph Davis
/
Jan 5, 2011
As we approach terabyte data volumes for IC designs at the 32/28 nm node, the de facto standard file formats, especially GDSII, are starting to look worn. Foundries have widely adopted a new standard, OASIS, for the post- tapeout flow and report at least a 10x file compression improvement. However, for 45 nm designs in 2009 there was still very little use of OASIS as a stream-out format from the design house to the foundry, or from the foundry to the mask house. Considering the data volume crisis emerging at 32/28 nm, OASIS will gain traction for tape-out. This article looks at the adoption trends by manufacturing steps – e.g design, post tapeout flow and mask manufacturing—and explains the factors influencing OASIS adoption.
[read more]
Fang Gong, Yiyu Shi, Hao Yu, Lei He
/
Jun 8, 2010
With technology scaling down to 90nm and below, process variation has become a major challenge for both design and fabrication. Among all types of circuits, Static Random Access Memory (SRAM) is particularly vulnerable to process variation, as it contains a large number of nearly minimum-sized devices with ever-decreasing supply voltage and reduced noise margin. To determine the performance of the SRAM cell under process variation, we need to estimate its parametric yield efficiently and accurately. Existing parametric yield estimation methods can be classified into two categories: performance domain methods which require extensive Monte Carlo simulation, and parameter domain methods which require the characterization of a yield boundary defined by performance constraints without using Monte Carlo simulations. In this article, we review the pros and cons of these methods, and use a six-transistor (6T) cell as a basis for evaluation and quantitative comparison.
[read more]
Llewellyn Marshall, Eric Foreman
/
Jun 8, 2010
As semiconductor technology continues to decrease in size, relative process variation grows. In order to create a robust design, one solution is for chip timing analysis to add margin for variation; however, this leads to a loss in possible processing performance. With the advent of statistical static timing analysis (SSTA), new methods have been developed to maximize product yield and improve timing accuracy. In this article, we describe an SSTA signoff timing methodology for 45nm ASICs using EinsTimer EinsStat. We further discuss timing closure techniques and experience with usage of this methodology.
[read more]
All Knowledge Center Offerings