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Parametric Yield Estimation for SRAM Cells: Concepts, Algorithms and Challenges

Tuesday, June 8, 2010
By: Fang Gong / Univ. of California, Los Angeles,
Yiyu Shi / Missouri University of Science and Technology,
Hao Yu / Nanyang Technological Univ.,
Lei He / Univ. of California, Los Angeles
Topic: Back-End — Sub-topic: Physical Design & Design Closure

Summary

With technology scaling down to 90nm and below, process variation has become a major challenge for both design and fabrication. Among all types of circuits, Static Random Access Memory (SRAM) is particularly vulnerable to process variation, as it contains a large number of nearly minimum-sized devices with ever-decreasing supply voltage and reduced noise margin. To determine the performance of the SRAM cell under process variation, we need to estimate its parametric yield efficiently and accurately. Existing parametric yield estimation methods can be classified into two categories: performance domain methods which require extensive Monte Carlo simulation, and parameter domain methods which require the characterization of a yield boundary defined by performance constraints without using Monte Carlo simulations. In this article, we review the pros and cons of these methods, and use a six-transistor (6T) cell as a basis for evaluation and quantitative comparison.

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