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Timing Closure in 45-Nanometer ASICs Using Statistical Static Timing Analysis Design Methodology

Tuesday, June 8, 2010
By: Llewellyn Marshall / IBM Microelectronics,
Eric Foreman / IBM Microelectronics
Topic: Back-End — Sub-topic: Physical Design & Design Closure

Summary

As semiconductor technology continues to decrease in size, relative process variation grows. In order to create a robust design, one solution is for chip timing analysis to add margin for variation; however, this leads to a loss in possible processing performance. With the advent of statistical static timing analysis (SSTA), new methods have been developed to maximize product yield and improve timing accuracy. In this article, we describe an SSTA signoff timing methodology for 45nm ASICs using EinsTimer EinsStat. We further discuss timing closure techniques and experience with usage of this methodology.

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