Verification Challenges and eDFM in Digital Designs

Summary

Article Text

Hazem Hegazy, PhD
Mentor Graphics, Wilsonville, OR, USA

In the past decade, the term "DFM" (design for manufacturing) was a massively used semiconductor industry buzzword. In reality, different people interpreted DFM to have different meanings. Some people thought of resolution enhancement technologies (RET) used in the creation of lithography masks for IC fabrication. Others viewed DFM from the design and physical verification side, which involved techniques such as critical area analysis, critical feature analysis, metal fill, litho hotspot detection, etc.

Don't get me wrong, all are correct…but look at its meaning…it's very general, and it blends two branches that are physically linked but intentionally separated-design and manufacturing. Consequently, the term DFM is a big umbrella that can accommodate many technologies that link manufacturing challenges with design techniques and constraints.

In recent years, another buzzword was introduced: electrical DFM or "eDFM." Although it includes the general term, DFM, the added "e" makes it a more specific definition referring to the electrical effects of manufacturing variation on parametric yield. For a designer, eDFM makes intuitive sense because it translates complex manufacturing concerns into a meaningful electrical property that he or she can understand and may be able to control.

eDFM in Digital Designs

Manufacturing issues, such as stress or lithographic variations of transistors, can lead to variation in electrical parameters such as drain-current and threshold-voltage. In the past, these variations were only considered in the analog design domain-they were second order effects for digital designs. The problem is that when these variations become large enough to have a significant impact on digital designs, they are difficult to deal with due to abstraction.

The digital flow was invented to get rid of transistors by going up a level to gates or cells to reduce complexity and allow more scalability and automation. For the concept of eDFM to introduce something meaningful to a digital designer, it has to talk their language, i.e., timing, power, leakage, etc. The challenge is not how to bring abstraction down to the transistor but how can we get eDFM up to the standard cells level?

In digital designs, some of manufacturing variability effects is captured through normal cell characterization techniques such as process, supply, and temperature corners. Others variations are related to design context and proximity to other objects, usually referenced as LDEs, or layout dependant effects. The main challenges that come with the latter are:

• • They are usually identified late in the design cycle when layout is already done.
  • Handling transistor level effects in huge digital designs is time consuming or exceeds the capacity of existing tools.
  • There is no way to represent subtle changes in delay, setup, hold times, etc., due to manufacturing variation within the cell abstraction.
  • There is often no mechanism for compensation and correction of these variations within the design database or the tool flow.
  • Ad hoc measures results in a complex, cumbersome flow.
• Let's take stress as an example. Transistor stress mainly is caused by nearby objects like poly and STI. The effect on transistor characteristics is either positive or negative, i.e., stress can make the transistor perform better or worse. Because stress affects the carriers' mobility inside of the channel, it also leads to other effects such as drain current and threshold voltage variations.

The transistor is a building block of digital cells that controls their timing behavior. So, if the transistors are behaving faster/slower than "usual" because of stress from other cells in their vicinity, it will make the entire cell delay less/more than whatever is characterized and captured in timing tables of that cell.

Using transistor-level simulators after the transistor-level LPE stage is one of the approaches followed today. However, I think it is problematic and useless, except for diagnostics reasons, because the data volume is massive and will take quite some time to simulate. In addition, and most importantly, when simulation finds a problem, this approach doesn't tell you what to do to solve it.

So, methodologies have to be developed to translate stress variations into current variations at the transistor level, then to translate transistor current variations into timing variation at the cell level. When this is accomplished, eDFM will have true meaning for digital designers because it will allow changes in manufacturing to be viewed on the design side as electrical effects at the right abstraction level (e.g, timing information). To be truly useful, the implementation of the methodology has to be fast and accurate enough to enable quick diagnosis over the entire design at different phases to allow corrective action as early as possible in the design process.