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Dawn at the OASIS

Summary

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As we approach terabyte data volumes for IC designs at the 32/28 nm node, the de facto standard file formats are starting to look worn. Foundries have widely adopted a new standard, OASIS, for the post-tapeout flow and report at least a 10x file compression improvement. However, for 45 nm designs in 2009 there was still very little use of OASIS as a stream-out format from the design house to the foundry, or from the foundry to the mask house. Considering the data volume crisis emerging at 32/28 nm, OASIS will gain traction for tape-out.  This article looks at the adoption trends by manufacturing steps – e.g design, post tapeout flow and mask manufacturing—and explains the factors influencing OASIS adoption.
Keywords: OASIS, OASIS.MASK, mask data preparation, mask economics

Usually, it takes a crisis to effect change in an established process. This is also true for the IC design and manufacturing industries, which are actively adopting a new format to represent layout and mask data. There have been two standard file formats use for layout data for many years. The de facto standard for tape-outs from the design house to the foundry has been GDSII, and the de facto standard for hand-offs from the foundry to the mask house has been either GDSII or MEBES. However, almost 10 years ago, it became clear that future technologies would bring with them a “data explosion”—a massive growth of layout and mask data that would seriously challenge the existing formats. As a reaction to this looming crisis, a new format was created to handle the future data needs – the Open Artwork System Interchange Standard, or OASIS®. Now, 10 years after the initiation of the effort and 5 years after the formal approval of the format by SEMI, we find that OASIS has been almost fully adopted in the parts of the post-tape-out flow, and is now emerging in the mask making and design flows.

With each new process technology node, the number of transistors per unit area doubles. However, the typical area of chips has remained approximately the same. Designers use this extra capacity to continually add more functionality that we want in our devices – BlueTooth™ this year, WiFi the next, streaming video the next, etc. As a result, the layout data for the chip design doubles along with each generation of technology.  
In addition to the direct doubling of layout density with each technology node, each new technology is also more difficult to manufacture than the next, so foundries have to employ such tricks as resolution enhancement technology (RET) to get the ever-finer features to print onto silicon. RET is a collection of corrections, additions, and modifications to the drawn layout that take into account the lithography system that will be used  to print the shapes on the silicon wafer. Each of these modifications makes the layout more complex and less repetitive and thus increases the size of the data files that describe the layout and direct how it will be rendered onto a mask, which is then used to create the actual silicon.
In 2001, RET was just beginning to be used. It was projected that RET techniques would be quickly adopted to improve the fidelity of printed shapes and that this adoption would drive an associated increase in the mask data file size [Figure 1]. The exact increase in file size is dependent both on the layout itself and how many of the design’s layers use the RET, but it was originally estimated at approximately another 50% per node. Since technologies are released approximately every 1.5-2 years, this means the IC industry would see an estimated 50% per year increase in mask data volume [1].

Figure 1. The amount of data for a given design grows as it progresses from layout data (“Drawn”) through metal fill and OPC (“RET”), to formatting for the mask makers (“Fracture”). Each step and the benefits of using OASIS are described in the sidebar “Layout data transformation from design to mask.”

In 2001, the industry looked at this astounding mask data growth and realized it would quickly exceed the capacity of the infrastructure used to make masks, including the formats used to store the layout data on disk. With surprising foresight, the industry came together and formed a working group to define a new format –OASIS. In 2005, when the OASIS format was officially approved, it was quickly supported by all of the major EDA vendors and some leading-edge companies such as Intel, TI, Fujitsu, NEC, and IBM had programs in place. OASIS looked primed for quick adoption.

Five years and two and half technology nodes later, is OASIS now the de facto standard for making masks? Not really. In fact, the first production mask making and inspection tools were only announced in early 2010 [2].
Is OASIS used for tape-out to the foundries?  Sometimes, for the most advanced nodes. Well, if OASIS isn’t in production for mask making – the application that was the impetus for its creation – and it isn’t the standard for tape-out to the foundries, is OASIS dead? Was the data explosion a mirage on the sand?  Not at all.
In reality, there are many steps between the hand-off from the design-house to a production mask set. Figure 2 depicts a simplification of the flow to show the major operations and hand-offs.  Using this simplified view of the flow, Figure 3 shows the results of a survey that examined the adoption of OASIS as a function of technology node at points B, “OPC”, and C, “Fracture” [3].  Adoption for the “tape-out” (point A in Figure 2) hand-off from the design house to the foundry and the hand-off from fracture to the actual mask tools has been negligible until this year.

2: High-level data processing flow, from design through mask delivery. Each hand-off is usually a separate software or hardware step, although the organizational hand-offs will differ for each company. For instance, some companies do fracture in-house and provide fractured data to the mask house, making the hand-off at C. Other companies hand off at point B and allow the mask house to do the fracture themselves.

3: Survey results showing OASIS adoption by technology node, broken down by the data-prep hand-offs. These results indicate that OASIS has been adopted by a significant fraction of companies doing OPC as early as 65nm, but that hand-off of fractured data in OASIS has lagged by as much as 2 process nodes. The OASIS format was introduced in 2005, during ramp-up of 65nm production for leading-edge companies. The non-zero adoption rate in older technologies reflects the fact that some manufacturers came on-line with those technologies at a much later date, when OASIS was widely available and proven in the production flow. 
The first thing that jumps out from this chart is that adoption of OASIS in the OPC step led that of the fracture step by two whole technology nodes. Since the mask data is largest after fracture, many expected that the hand-off from fracture to mask making would have the fastest adoption.  Why was the RET step, which deals with smaller files, the first place where OASIS was adopted?

Diffusion of Innovation – pain, gain, and relationships
As in the adoption of any new technology, the new technology must present a solution to a known problem in order to gain acceptance. The rate of adoption is related to

• The level of pain and risk associated with continuing the status quo
• The gain associated with adopting the new technology
• The costs and risks associated with changing to the new technology
• Environmental factors that can either accelerate or inhibit adoption of the solution

Cost of inaction – The first aspect is the consequence of not changing and just adapting to the file size growth. The direct, measurable pain of not changing is the need to store and process very large files. The original ITRS estimate of file size growth was 50% per year. The cost of hard disk storage and international internet bandwidth (for transfers) have both shown a consistent decrease of at least 30% per year. However, by the time the OASIS and OASIS.MASK standards were released in 2005, the file size growth rate had been revised down to 30% per year – meaning that the direct cost of inaction was roughly flat. Thus, while the file sizes might be exploding, the direct cost of storing and transferring them was not!

However, the less measurable effect of the growing file sizes is the fact that every task associated with processing those files is affected. Very large files require longer to process, longer to load into viewing tools, longer to review, longer to transfer, etc. There are at least four points in the typical process flow where an engineer needs to load the layout data into a viewing tool and manually review the layout: tape-in, post-OPC verification, post-MDP verification, and final customer mask review. At each of these steps, the data size, and therefore the hardware and time requirements for viewing, grows. Also, while the size of these files grows continuously, the hardware on which the engineers view the files is usually purchased no more frequently than every 18 months. Thus, the hardware that is actually in use for engineering review naturally lags the technology curve and one can almost guarantee that engineers are continually waiting for new hardware on which to review the latest files. These effects are real, but difficult to measure directly.

Risk of inaction – The risk of not changing from the legacy formats is that, eventually, one of the layouts will actually exceed the capabilities of the legacy file formats. While each of the formats has its own limitations, some of the relevant limits are how many shapes can be represented, grid size, offsets. Since these files are used to generate the masks for silicon processing, the result of violating one of the file limits is that the chip would literally not be manufacturable. At each node, the foundry can estimate the probability of this happening and weigh the consequences of not being able to manufacture a chip versus the costs and risks associated with transitioning to the new format. 

Benefits of migration – File size, processing time, engineering review time. For the RET step, the file size is reduced ~5x with OASIS. Since there is a single input and a single output, this benefit is direct. Processing time is not dramatically affected. Engineering time to review OASIS files is shorter, but the benefit is highly variable depending on the application. For the fracture step, the storage and processing benefits of full migration can actually be very high, as full migration would eliminate the need for multiple file formats. Mask houses typically need to create and store up to three different versions of the data in order to make maximum use of their equipment.

Cost of migration – This is the upgrade cost plus the cost of qualifying the new format in the manufacturing flow. For RET, the upgrade cost is negligible, as RET and associated software are updated on a quarterly basis and are typically purchased on a subscription model. Qualification can be achieved in parallel with the existing flow, so the over-head is small. For OASIS to be used as the input to the mask making tools, the mask tools must be able to accept it as input. As shown in Figure 2, there are three types of relevant equipment – writer, inspection, and metrology. Even if the mask house has only one machine of each type, three different hardware vendors must upgrade their tools to fully migrate a single technology node to the new format. Also, since hardware vendors typically only put new features on new equipment, new hardware must be purchased in order to obtain support for the new format, thus ensuring a long adoption cycle that is tied to equipment purchase.
Risk of migration – The probability of data loss or corruption cannot be predicted, and can only be mitigated by a lengthy prove-out period.

Environmental factors – This refers to the technology development cycle. One of the first steps in technology development is to run test chips for process development. These test chips need masks. Therefore, the mask process needs to be operational when the new technology is in its infancy, meaning that mask hardware vendors must have their products ready for the next node even earlier. It is becoming more common for there to be new mask writers for each technology node. In the software industry, customers get continuous updates to a purchased piece of software. However, the hardware typically requires a new purchase in order to acquire upgrades. Therefore, the mask-making hardware must be in place much earlier than the OPC or pre-OPC software and is updated less often. Furthermore, mask hardware manufacturers will only make an investment to support a new format if their customers demand it and their customers, the mask houses, will necessarily take a significant amount of time to qualify and gain confidence in the new format.

From the starting point of having full support in the EDA software, the RET hand-off became the proving ground to evaluate the efficacy and value of OASIS. Once proven in this context over a technology node, the mask manufacturing industry could begin evaluation in earnest, knowing that their customers, the foundries, could work with the new format. Using the onset of software support at as the beginning of OASIS availability, 18 months for proving in a technology node, and a two year model of technology development, it is natural that mask tools are just now starting to support OASIS, four years after it was fully supported by the EDA industry.  This process of downstream migration will naturally continue, as the new format has proven to add value throughout the flow.
A summary of the relative benefits of switching to OASIS for the RET and fracture steps, and the accompanied complexity of doing so, is shown in Table 1.

Table 1: Summary of benefits and complexity for adopting OASIS format to replace existing legacy formats in the RET and fracture processes.

We anticipate a gradual expansion of the full adoption of OASIS. But there are benefits even for hybrid flows, in which both OASIS and legacy formats are used. Figure 4 shows the relative runtime for several different mask manufacturing flows, from the current state to a full OASIS deployment.

Figure 4: Data processing effort for mask manufacturing with increasing extent of machine support for OASIS.MASK. The basic assumption is that commonly three formatting steps are conducted (Fracture 1, Fracture 2, Fracture 3). OASIS.MASK introduction has the potential to reduce the overall effort by 3x.

In “Transition 1,” only the inspection tools support OASIS.MASK. In “Transition 2,” the inspection tools and one of the mask writing machines support the new format, requiring only one translation between formats. The chart shows there is clear value to continuing the migration from legacy formats to OASIS.MASK in the mask industry and to OASIS in the remainder of the post-tape out flow. The maximum benefit— ~ 3x reduction in processing time and ~6x reduction in file size is—obtained when all machines support OASIS.MASK natively.
In the design area, we expect OASIS to be used increasingly in the chip assembly/chip finishing stage, especially for large designs. This is the area where reducing file size can improve the over-all infrastructure burden and increase turn-around-time for such activities as physical verification, file merging, etc. Other stages of the design process may benefit from other aspects of the OASIS format, such as encryption and the structure of the data storage format (indexes, etc), the value of these features will depend on the specific design flow and design types. 

The OASIS formats offer at least 10x data volume reduction for the design and post-OPC data and over 4x for fractured data. The new formats were quickly support by the EDA companies, and adoption of the new format in production flows is progressing – led by the post-OPC data hand-off starting at the 65nm node – where more than half of those surveyed are using it.
The deployment of OASIS and OASIS.MASK is progressing, but has been delayed by economic and technical factors. Yet even partial deployment, along with format translation, can offer a significant benefit in data processing time and file size reduction that will meet the post-tape out and mask making demands of designs at 22nm and below.

DRAWN: Most Design-level layouts are created by combining a set of standard cells, each of which implements a given function, thereby creating a hierarchical data structure. Especially in digital designs, the same standard cell may be used 1000’s of times in different parts of the circuit. Since it is the same layout cell in all cases, the data can be represented by a single instance of the cell and a list of where that cell will be placed. All layout file formats take advantage of this hierarchical data structure to reduce the total file size. In addition, some layout file formats, such as OASIS, can recognize repeated patterns that are not design elements (say, an arbitrary group of polygons that are repeated throughout the layout) and also store them compactly. Thus, design layout data is highly compressible. For a layout like the one depicted in Figure 1,  the OASIS format get up to nearly 200x compression vs the less advanced GDSII format. More typical compression results for OASIS vs GDSII on design data is about ~30x compression.

Figure 1. Shapes in a basic layout, before any OPC is applied.

RET: Once the design layout meets the foundries specs for incoming quality, it is then heavily processed to transform the drawn patterns so they will produce the desired shapes on the silicon wafers.  The first part of the transformation is to add features and corrections to account for limitations and variability of the manufacturing process. The two most widely-known types of corrections are dummy fill and optical proximity correction. Dummy fill adds shapes to empty portions of the layout to create a uniform density of shapes across the entire layout.

Figure 2. Layout with metal file and SRAFs.

These are shown in dark blue.  Optical proximity correction uses a number of techniques, including non-printing “sub-resolution assist features” (SRAFs, shown in light blue) and pre-distortion of the shapes to accommodate the distortion that will occur in the lithography process. These techniques are dependent both on the local features and on the features in the surrounding area. As a result, two identical cells that are placed in two different locations in the layout may get treated very differently by the RET algorithms. Since the placed cells are no longer identical, they must be represented independently, thereby increasing the file size. As a result of both the added geometries and the loss of pattern repetition, both GDSII and OASIS files are much larger after RET is applied. A post-RET layout, as shown Figure 2, has file sizes ~15x larger than the design files and the compression ratio between GDSII and OASIS falls to ~6x.

Fracture: The final step before giving the layout data to the mask making and inspection machines is to transform the layout data into a format that the mask making machines understand. This format is called “fractured,” since the shapes created by the RET processing are “fractured” into a set of rectangles or trapezoids that can be processed independently, as shown in Figure 3.

Figure 3. Layout with metal fill, SRAFs after the fracturing step.
This step again increases the file size of the layout because it increases the number of shapes in the database. Depending on the fracturing algorithm, this step can also decrease the hierarchy and repetitive nature of the patterns, again increasing the file size.

• http://www.itrs.net/reports.html, ITRS Reports, years 2001, 2003, 2005, 2007, 2008
• Public announcement at the TSMC Technology Symposium, 2009, Santa Clara CA.
• J. Davis, S. Schulz, S. Fu, Y. Tong “Deployment of Oasis in the Semiconductor Industry – Status, Dependencies And Outlook,” Proc. of Proc. of SPIE Vol. 7545, 26th European Mask and Lithography Conference, 2010.

Author Bio
Joe Davis' career in the IC industry spans over 20 years at high-profile companies such as Analog Devices, Texas Instruments and PDF Solutions. He has worked on both sides of the EDA relationship, both designing ICs, and developing tools for IC designers and manufacturers. He is now Mentor's Product Manager for Calibre interactive and integration products where he applies his expertise in data visualization and engineering workflow. Prior to joining Mentor Joe was the senior product manager for yield simulation products at PDF Solutions where he managed semiconductor process-design technologies and services, including yield simulation and analysis tools.  Joe earned his BSEE, MSEE and Ph.D. in Electrical and Computer Engineering from North Carolina State University.