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3D ICs with TSVs – Design Challenges and Requirements
Thursday, June 2, 2011
/ Cadence Design Systems
: Test & Packaging
As demands accelerate for increasing density, higher bandwidths, and lower power, many IC design teams are looking up – to 3D ICs with through-silicon vias (TSVs). 3D ICs promise “more than Moore” integration by packing a great deal of functionality into small form factors, while improving performance and reducing costs. 3D IC packages may accommodate multiple heterogeneous die -- such as logic, memory, analog, RF, and micro-electrical mechanical systems (MEMS) -- at different process nodes, such as 28nm for high-speed logic and 130nm for analog. This provides an alternative to system-on-chip (SoC) integraton, potentially postponing an expensive move to a new process node for all of the functionality developers want to place in a single package.
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