Designer Track brings together IC designers and embedded software developers from across the globe. Designers and software developers from Intel, IBM, Samsung, TI, Toshiba, Qualcomm, AMD, Freescale, and other leading IC companies will present their design experiences on effective design flows, methods, and tool usage. Designer Track will include presentation/poster sessions, panels and invited talks. It offers a unique opportunity to network with and learn from other industry experts. There is no other way to improve your “design IQ” in such a short amount of time.
Designer Track submissions may describe the overall design and/or application of tools for creating the hardware and/or software components of a novel electronic system. Regular submissions will be accepted in the following categories:
1. Front end silicon design (FE): Front end architecture, design and verification of System-on-Chip (SoC) including major components such as CPU, GPU, and DSP.
2. Back end silicon design (BE): Back end design and verification of SoC, major sub-systems and constituent components (CPU, GPU and DSP).
3. Embedded Systems and Software (ESS): Design and modeling of entire embedded systems and associated software.
Designer Track regular submissions are in the form of a slide presentation.
- Submissions are limited to 15 total slides (12 + 3 submission-specific slides). (Remember that a DAC presentation is 14 minutes long.)
- Submissions must be in .PDF or PowerPoint format.
- If in .PDF, please ensure that the speaker notes are visible.
- Consistent with DAC policy, company logos may appear only on the title slide.
- Slide 1: Title, author names and affiliations
- Slide 2 (only for submission): Name, affiliation, phone number and email addresses for all authors. Authors MAY NOT be added after the January 23 deadline, so be sure to list all authors in the initial submission.
- Slide 3 (only for submission): One to two-paragraph abstract
Links to example slide presentations from 2013 can be found here.
|November 7, 2013
||Submission Site Opens
|January 23, 2014
||Submission deadline. Please visit here for Designer Track submission link.
||Notification to accept as poster, accept as presentation, or reject.
||Submission deadline for draft of final posters and/or presentations and speaker bios (for full talks only). All material will be reviewed by Session Chairs.
||Deadline for Session Chairs to communicate poster and slide presentation feedback to authors.
Presentation and Poster Format
Based on the program committee evaluation Designer Track submission may be accepted in either i) presentation and poster or ii) solely poster form. Designer track presentations are 15 minutes (including 1 minute for Q and A). Each author is allocated a 42” tall x 36” wide area for a poster. A Best Presentation award will be selected from the Designer Track presentations. The award will be based on both the quality of the submission and the DAC presentation itself. Designer Track poster sessions will run for 1 1/2 hours, and will include 20-30 posters. Poster authors are welcome to distribute additional material to interested attendees. Such material can include extended abstracts and whitepapers.
Accepted Designer Track presentations and posters are NOT included in the DAC proceedings. However, accepted Designer Track submissions (both posters and presentation slides) will be made available on the DAC website after the conference as a part of the DAC Archives.
D1. Front end silicon design (FE):
D1.1: Architecture exploration/design/optimization of CPU, GPU, DSP and accelerators
D1.2: Memory architecture design
D1.3: Sub-system (graphics, multimedia, modem) design/optimization
D1.4: System and high-level hardware synthesis
D1.5: Power/area/performance trade-offs and low-power design
D1.6: Bus and network communication
D1.7: Logic simulation
D1.8: Validation, test planning, and coverage
D1.9: FPGAs and emulation
D1.10: Formal verification
D2. Back end silicon design (BE):
D2.1: Physical synthesis tools and techniques
D2.2: Clock tree design and optimization
D2.3: Power distribution network design and optimization
D2.4: Timing and circuit analysis/optimization
D2.5: Reliability analysis and optimization
D2.6: Interconnect simulation and analysis
D2.7: Physical design and manufacturability
D2.8: Manufacturing test and silicon debug
D2.9: Analog, mixed-signal, and RF design
D2.10: Custom, standard cell, and FPGA design flows
D2.11: 3D silicon technology and integration
D2.12: Tool control and integration
D3. Embedded Systems and Software (ESS):
D3.1: System architecture exploration/design/optimization
D3.2: Software specification/models/frameworks
D3.3: Virtual platform and simulation environments
D3.4: Design/application of compilers/programming aids
D3.5: Design/application of operating system (including RTOS)
D3.6: Virtual machines and run time environments
D3.7: Security for embedded systems and software
D3.8: Validation, test and verification
D3.9: Design methodologies and flows
D3.10: Case studies
A. To spare authors the many hours of preparation associated with a regular manuscript submission, Designer Track submissions are in the form of slide presentation. Authors of accepted submissions will be invited to present a poster during a Designer Track poster session. Authors of particularly high-quality submissions will be invited to present their work during a Designer Track session at the conference. More details can be found at the top of the page under Submission Guidelines.
A. Designer Track focuses on the hardware designers and embedded software developers, in short the EDA tool users. This complements DAC’s strong research focus on algorithms and methodology. The Designer Track aims to illustrate both benefits and challenges of tool usage, and provides educational and networking benefits for both designers and tool developers. The topics are at the interface between design and automation, an area that until now has been under-represented in EDA.
The Designer Track is intended specifically for practitioners. Whether you are an EDA tool user, hardware or software designer, application engineer or a consultant, the Designer Track is an ideal place to meet and share your experiences.
A. Designer Track provides a vendor-agnostic and objective forum for designers and EDA users. To this end, Designer Track submissions that are essentially marketing material will be rejected. On the other hand, joint customer/vendor submissions written from the perspective of the designer/developer are encouraged and are a valuable part of the Designer Track.
Sure! Links to example slide presentations from 2013 can be found in here.
A. No. We made exceptions to this policy in past years, but it resulted in many problems, including introducing new conflicts of interest with reviewers on the Program Committee.
A. No. While we sympathize with your situation (many of us have been there), we have a tight schedule and are unable to accommodate late submissions. Please obtain appropriate legal, copyright, and any other needed permission well ahead of the submission deadline.
A. Designer Track posters are presented during Designer Track poster sessions. Designer Track presentations are oral presentations similar to those in the DAC research track. Designer Track presentations are scheduled in sessions that run parallel to the rest of the DAC program and also include a poster session at the end of the slides presentation session.
A. Authors of accepted presentations will be allocated 15 minutes in a Designer Track session; 14 minutes for the presentation and 1 minute for Q/A and transition to the next speaker. Similar to the DAC Research Track, 30 minutes is reserved at the end of each session for a dedicated poster session. This provides an opportunity for extended discussion with interested members of the audience. Designer Track sessions will be 90-120 minutes in length (four 15-minute presentations + 30 minutes for a poster session or six 15-minute presentations + 30 minutes for a poster session).
A. Designer Track seeks contributions that highlight the benefits and challenges of design tool usage. Tools can be from EDA vendors or developed in-house; while flows can be built around a single tool or multiple tools. We specifically seek contributions from system engineers, hardware designers, embedded software developers, application engineers, and vendor/customer teams. Documented tool use may target electronic design and system design at all levels of abstraction and across all application domains.
A. Designer Track program committee consists of industry experts that collectively represent years of design, tools and methodology experience.
A good Designer Track presentation addresses innovative tool use coupled with high-quality results. The considerations used by the program committee in acceptance decisions include:
- Significance of results supported by clear, measurable criteria, including, but not limited to: improved quality of silicon, decreased complexity, and reduced time-to-market.
- Level of innovation in tool use, e.g., utilizing one tool to obtain results that aid another tool, writing scripts to combine tools, user-facing enhancements, intelligent data management. A submission should not mirror the help section in the tool's user manual, but instead address a creative way of using the tool.
- Ability to overcome design challenges such as scalability, integrating IP, and bridging front-end/back-end gaps.
- Validation of the proposed techniques using real designs, case studies, or established benchmarks.
- Discussion of the conceptual limitations of tools and suggestions for future tool improvement. Solid technical contributions should address both the strengths and the weaknesses of the approach.
- Quality of material including writing, illustrations, and organization.
- Product marketing material is inappropriate for the Designer Track.
A. Yes. DAC conference registration is required to participate in the Designer Track. This registration also provides access to the exhibition floor, keynotes, and other areas of the DAC conference. Designer Track authors are eligible for the same discounted registration offered to speakers in the DAC research tracks.
A. Remember that your slides must be presented in 14 minutes. Presenting meaningful content in a short time is challenging and requires careful thought and planning. You may optionally include some backup slides that describe additional material that you would include on an accompanying poster.
Please visit Template Download Options for presentation templates and additional information on how to prepare your slides. You are not required to use a DAC slide template, but this is a good way to avoid potential issues. Example presentations from previous years can be found in the DAC Archives.
A. Please address any unanswered questions to 51st DAC Designer Track Chairs, Karam S. Chatha, Qualcomm Research and Dan Bourke, Cadence Design Systems.