Synopsys Partner Breakfast: Optimizing Implementation of Performance- and Power-Balanced Processor Cores
Monday, June 3, 2013
Time: 7:15 AM — 8:45 AM
Hilton Grand Ballroom H
Low-Power Design and Power Analysis
Hear from experts about engineering trade-offs and best practices when using Design Compiler Graphical and IC Compiler to implement an ARM® Cortex®-A15 dual-core processor optimized first for performance, then power, and a Cortex-A7 quad-core processor optimized first for energy efficiency, then maximum speed.