SESSION 2: DESIGNED IN TEXAS
Physical Design I
Tuesday, June 4, 2013
Time: 10:30 AM — 12:00 PM
|Moderator: ||Jonathan DeMent - IBM Corp., Austin, TX|
Designers from AMD, Freescale, and Everspin talk about physical design methodologies on CPU cores, SoC power management with biasing, and Magnetoresistive RAM.
Physical Design Methodologies on AMD’s CPU Cores
This presentation will cover the physical design methodologies and CAD flows used on AMD’s low-power (Jaguar) and high-performance (SteamRoller) CPU cores. Both CPU cores used a wide variety of construction techniques including full-custom macros, custom-placed blocks and synthesis/P&R. Each of these methodologies along with corresponding tool flows will be discussed. We will also give an overview of the tools and methodologies used for static timing, IR, electro-migration, power consumption analysis, leakage recovery and clock/voltage domain crossing. The presentation will highlight some of the unique tool flows developed around in-house and industry-standard CAD tools.
|Speaker: ||Mahesh Sharma - Advanced Micro Devices, Inc., Austin, TX|
SoC Power Management Using Biasing Techniques
This presentation summarizes various techniques used on 90nm & 55nm designs to reduce leakage power by 75% on 90nm and 50% on 55nm designs with minimal performance penalty. It will also describe the tool limitations encountered in constructing these SoC’s. Some of the additional complexities seen at 40nm and 28nm will be covered inherent in the larger variations of the smaller geometries.
|Speaker: ||Dave Tipple - Freescale Semiconductor, Inc., Austin, TX|
Design, Technology, and Commercialization of Magnetoresistive RAM
Everspin's Magnetoresistive Random Access Memory (MRAM) combines magnetic storage elements with a standard CMOS logic process to obtain the benefits of non-volatility, RAM speed and unlimited read/write endurance, a combination not found in other existing volatile or non-volatile commodity memory technologies. The first generation Toggle MRAM has been widely adopted in storage systems, industrial computing, cognitive computing, automotive, and aerospace application. Everspin recently introduced the second generation Spin-Torque MRAM (ST-MRAM), announcing fully functional 64Mb DDR3 ST-MRAM working samples that offer a new persistent memory solution for non-volatile buffers and caching applications as well as deliver a new nanosecond-class, gigabyte-per-second non-volatile storage tier. This presentation will discuss technology-circuit co-design considering ST-MRAM technology attributes, read and write circuit characteristics, and architecture considerations in MRAM chips.
|Speaker: ||Syed M. Alam - Everspin Technologies, Inc., Austin, TX|