SESSION 4: DESIGNED IN TEXAS
Design Methodologies from ESL to Fault-Tolerance
Tuesday, June 4, 2013
Time: 4:00 PM — 6:00 PM
|Moderator: ||Ed Nuckolls - Freescale Semiconductor, Inc., Austin, TX|
Methodologies for addressing today's complex designs will be presented by designers from LSI, Asset-Intertech, Freescale, and Maxim. These methodologies include transaction-level modeling with SystemC, test and design for test, fault-tolerant architecture, and a mixed-signal methodology.
Adding SystemC TLM to a RTL Design Flow
Over recent years the EDA community has embraced the Electronic System Level (ESL) design flow, SystemC, Transaction Level Modeling (TLM) and High Level Synthesis (HLS). Today all major EDA vendors provide the tools needed for an ESL design-flow. With these tools in place design teams need to develop a flow that provides early return on investment, creates an ESL foundation and do this with minimum disruption to active designs and design-flow.
This presentation will explore the most common ESL use-cases and their relation to traditional SoC design flow. Some use-cases focus on single functional blocks, others model major sub-systems, and the virtual system prototype use-case models the complete system. Models of IP blocks are characterized by their functional and performance accuracy and their speed of execution. A model used by a specific use-case will, by necessity, emphasize or de-emphasize these characteristics. Models for a virtual system prototype will emphasize functional accuracy and de-emphasize timing accuracy. Models for performance analysis will emphasize timing accuracy and de-emphasize data and non-performance-critical functionality.
An example ESL design-flow identifies the opportunities and challenges as a team’s traditional RTL design-flow evolves to an ESL design flow that includes architecture, hardware, design-verification and software.
|Speaker: ||Bill Bunton - LSI Corp., Austin, TX|
Test and Design-for-Test
|Speaker: ||Al Crouch - ASSET InterTech, Inc., Austin, TX|
Design of Fault Tolerant Architecture in System on Chip
This presentation will describe a modified TMR methodology (Triple Module Redundancy) that is suitable for large SoC designs. The techniques achieves Fault Tolerant SoC designs without the prohibitive costs of a full TMR scheme.
|Speaker: ||Rekha Bangalore - Freescale Semiconductor, Inc., Austin, TX|
Mixed-Signal Methodology for First Pass Success - Maxim’s InTune Digital Power
We will present an overview of the design methodology used to develop the Maxim InTune Digital Power products in Austin. The presentation will include specification development, RTL design, analog circuit design, modeling, and verification. Emphasis will be on mixed-signal verification and chip build and assembly. The talk will include the first generation product and discuss how the design flow enabled the quick development of the second derivative product. We will also discuss FPGA emulation and how it was used in the development.
|Speaker: ||Scott Herrington - Maxim Integrated, Austin, TX|