Wednesday, June 5, 2013 | 9:00 AM — 11:00 AM
| 18D
Topic Area:
Verification and simulation
Wednesday, June 5, 2013 | 2:00 PM — 4:00 PM
| 17AB
Topic Area:
System Level Design and Communication
Wednesday, June 5, 2013 | 2:00 PM — 4:00 PM
| 9ABC
Topic Area:
High-Level and Logic Synthesis