Wireless Algorithm Validation from System to RTL to Test
Wednesday, June 5, 2013
Time: 2:00 PM — 4:00 PM
System Level Design and Communication
|Speakers: ||Dmitry Melnik - Aldec, Inc., Henderson, NV|
| ||Sangkyo Shin - Agilent Technologies, Inc., Santa Rosa, CA|
Agilent Technologies and Aldec will co-host a session on how to validate a digital signal processing algorithm for both floating and fixed point levels. Attendees will gain insight on cross-domain approach to traditional FPGA design flow and learn how to validate FPGA design for leading edge wireless and radar system with a system-level simulation tool integrated into the traditional hardware design flow.
Attendees will gain valuable, practical skills with the following tools and equipment:
- Agilent SystemVue as a programming environment to simulate and verify system performance prior to realizing a dedicated hardware implementation.
- Co-simulation interface with Aldec Riviera-PRO for validation of functional blocks described in SystemVue hardware design library.
- HIL (Hardware in the Loop) to accelerate both design validation and test coverage, saving additional development time.