SESSION 1: TECHNICAL PANELS
Advanced Node Reliability: Are We in Trouble?
Tuesday, June 4, 2013
Time: 10:30 AM — 12:00 PM
Test and reliability
|Moderator: ||Andrew B. Kahng - Univ. of California at San Diego, CA|
|Panelists: ||Vassilios Gerousis - Cadence Design Systems, Inc., San Jose, CA|
| ||Kee Sup Kim - Samsung, Yongin, Republic of Korea|
| ||Martin Saint-Laurent - Qualcomm, Inc., Austin, TX|
| ||Michael (Misha) Khazhinsky - Silicon Laboratories, Inc., Austin, TX|
| ||Valeriy Sukharev - Mentor Graphics Corp., Freemont, CA|
As designs move to 20nm and 14nm, reliability issues have become increasingly complex. EM is now a critical design sign-off requirement. ESD failures can significantly degrade the yield. Wear out-related defects impact circuit margining and lifetime requirement for critical applications. This panel will discuss the reliability challenges and debate what would be the best ways for designers, foundries, and EDA vendors to define and develop advanced circuit checks and design sign-off at these advanced nodes.