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DAC 2013 AUSTIN, TX | JUNE 2-6
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Paper Sessions

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SESSION 3: PAPER SESSIONS
Emerging Mapping and Management Algorithms for Parallel Embedded Systems

Tuesday, June 4, 2013  |  10:30 AM — 12:00 PM   |  11AB
Topic Area: Embedded Software

SESSION 4: PAPER SESSIONS
Lay it out, Analog!

Tuesday, June 4, 2013  |  10:30 AM — 12:00 PM   |  13AB
Topic Area: Analog/Mixed-Signal/RF Design

SESSION 6: PAPER SESSIONS
Transformations in FPGA Design and Productivity

Tuesday, June 4, 2013  |  10:30 AM — 12:00 PM   |  15
Topic Area: High-Level and Logic Synthesis

SESSION 9: PAPER SESSIONS
Teaching the Old Backend Compiler Dog New Tricks

Tuesday, June 4, 2013  |  1:30 PM — 3:00 PM   |  11AB
Topic Area: Embedded Software

SESSION 10: PAPER SESSIONS
Answers to Some of Your Embedded System Design Questions

Tuesday, June 4, 2013  |  1:30 PM — 3:00 PM   |  13AB
Topic Area: Embedded Design Methodologies

SESSION 11: PAPER SESSIONS
Don't Fret About Your FinFet: Physical Design in 14nm and Beyond

Tuesday, June 4, 2013  |  1:30 PM — 3:00 PM   |  14
Topic Area: Physical Design

SESSION 12: PAPER SESSIONS
Taming the Beast: Coping with Imperfect Design and Silicon Defects

Tuesday, June 4, 2013  |  1:30 PM — 3:00 PM   |  15
Topic Area: Test and reliability

SESSION 16: PAPER SESSIONS
Better to be Proactive or be a Slacker in NoC Design?

Tuesday, June 4, 2013  |  4:00 PM — 6:00 PM   |  11AB
Topic Area: System Level Design and Communication

SESSION 17: PAPER SESSIONS
Off-the-Shelf Techniques for Quantum and Bio Circuits

Tuesday, June 4, 2013  |  4:00 PM — 6:00 PM   |  13AB
Topic Area: Emerging Design Technologies

SESSION 18: PAPER SESSIONS
Enlarging the Universe: Innovative Exploration for RTL and High-Level Synthesis

Tuesday, June 4, 2013  |  4:00 PM — 6:00 PM   |  14
Topic Area: High-Level and Logic Synthesis

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Design Automation Conference Sponsors IEEE Solid State Circuits Society Electronic Design Automation Consortium CEDA - IEEE Council on Electronic Design Automation SIGDA Special Interest Group - Design Automation