A Formal Approach to Low-Power Verification
Wednesday, June 5, 2013
Time: 9:00 AM — 11:00 AM
Verification and simulation
|Organizer: ||Rob van Blommestein - Jasper Design Automation, Inc., Mountain View, CA|
|Speaker: ||Lawrence Loh - Jasper Design Automation, Inc., Mountain View, CA|
The session addresses how formal methods meet the complex challenges of verifying power-aware SoC designs, which require power optimization throughout the design flow. It demonstrates how formal eases and speeds the analysis, verification and debug at both architecture and RTL levels, ensuring that power management circuitry not only functions correctly, but also does not corrupt the SoC’s functionality.