Track 2, Part II - SystemVerilog Verification: Getting Started with UVM, the Universal Verification Methodology
Thursday, June 6, 2013
Time: 2:00 PM — 5:30 PM
Verification and simulation
|Organizer: ||Lori Sanine - Doulos, San Jose, CA|
|Speaker: ||John Aynsley - Doulos, Ringwood, United Kingdom|
(Includes a 30-minute coffee break)
This session will get you started with UVM, the Universal Verification Methodology for SystemVerilog. UVM is an Accellera standard SystemVerilog class library that enables verification code reuse and encourages best practice when building constrained random verification environments.
This session will take a very practical approach to UVM, teaching some of the most common and important features of UVM by presenting a series of fully detailed code examples. This session is aimed at hands-on engineers who want to start writing UVM code themselves and are looking for some specific advice on the best place to start, the right UVM features and coding idiom to use, and the pitfalls to avoid.
This track is taught by Doulos CTO John Aynsley, winner of the Accellera Systems Initiative 2012 Technical Excellence Award for his contribution to the development of language standards.