Panel: FinFETs - Challenges in Deployment
Tuesday, June 4, 2013
Time: 11:30 AM — 1:30 PM
Austin Convention Center, Fourth Floor, Ballrooms
Low-Power Design and Power Analysis
|Panelist: ||Vinod Kariat - Cadence Design Systems, Inc.|
Cadence will host a panel of industry leaders discussing the challenges in deploying advanced node designs including FinFETs. Panelists will debate issues around process development, optimization interplay, and performance, power and density trade-offs. Participants include leaders from such companies as TSMC, ARM, Texas Instruments and Cadence. Join us for an informed and lively discussion, served with a delicious lunch. Doors open at 11:30am.