Tutorial 4: A Practical Guide to Packaging IP and Assembling SoCs Using the IP-XACT- IEEE1685 Standard
Monday, June 3, 2013
Time: 11:00 AM — 1:00 PM
System Level Design and Communication
|Organizers: ||David Murray - Duolog Technologies Ltd., Galway, Ireland|
| ||Kathy Werner - Southwest Reuse, Austin, TX|
|Speakers: ||David Murray - Duolog Technologies Ltd., Galway, Ireland|
| ||John Eaton - Ouabache Designworks, Vancouver, WA|
| ||Vasant Kumar Easwaran - Texas Instruments India Pvt. Ltd., Bengaluru, India|
| ||Mark Noll - Synopsys, Inc., Portland, OR|
| ||Kamlesh Kumar Pathak - STMicroelectronics, Greater Noida, India|
| ||Sylvain Duvilliard - Magillem Design Services, Cannes, France|
A practical guide to packaging IP and assembling SoCs using the IP-XACT- IEEE1685 Standard. This all-day tutorial will appeal to those new to the IP-XACT- IEEE1685 standard as well providing additional insight into more advanced IP-XACT topics. The tutorial will be presented by IP-XACT experts and will begin with a brief introduction to IP-XACT, followed by a deeper dive of the core IP packaging and design/assembly metadata concepts of IP-XACT and concludes with an examination of the typical flows that can utilize this metadata.
Attendees will initially be through typical IP Packaging metadata e.g. components, bus definitions, bus interfaces and HW/SW interface representation. The focus will then move to integration-oriented topics and explore how hierarchical designs are represented and connected. Some advanced integration topics are introduced that explore how system-memory mapping are represented as well as how configurability is addressed. The final section then explores how this component and design metadata can be processed and presents several different example flows.
The presentation technique will focus more on visually presenting the IP-XACT concepts rather than walking through XML snippets.
is CTO of Duolog Technologies and has been involved in chip design for over 20 years. His career has spanned IC design & verification, software development, and EDA solutions and he has written and presented many papers across a wide range of topics, from algorithmic IP, verification methodologies to IP reuse and integration and contributed to on a book titled ‘ESL models and their Applications’. He is currently involved in IP standards development in Accellera’s VIP and IP-XACT technical committees and chairs the IP-XACT Best-practice working group. In Duolog, he is championing IP automation and integration solutions and in his spare time runs a blog called ‘Integration Insights’ where he continues to evangelize integration methodologies.
retired from Hewlett-Packard after 29 years as an ASIC and PCA Design Engineer and now consults on design-for-reuse issues and techniques. He holds a BSEE from Purdue University and maintains the SoCGen Open Source tool projects on opencores.org
Vasant Kumar Easwaran
has been with TI for the past 13 years, currently working in the SoC Architecture team, responsible for delivering executable specifications for Automotive SoCs. He works on IP-XACT creation for registers and IP entities and creation of tools/flows to automate creation of software, customer documentation, RTL and DV test suites. As part of his work, complex Automotive SoCs with 100s of IPs were represented in IP-XACT-IEEE1685 form, generation of software header files with millions of lines of code/comments were automated, generation of RTL and DV test suites for connectivity of non-standard IP interfaces (100s of signals) were automated via executable specifications.
is a Senior R&D manager who is responsible for IP reuse tools. He is an active member of IP-XACT standardization effort since its inception. Mark is also the current chair of the IP-XACT schema working group.
Kamlesh Kumar Pathak
has 10 years of professional experience in the semiconductor industry around System level design tools, flows and methodologies. Kamlesh is currently working as a Senior Project Manager and leading a system level design team with 25+ engineers located globally which manage tools and methodologies around IP-XACT to automate IP packaging, model generation, test bench generation, VSoC/SoC integration and verification to accelerate the complete system level design flow. Kamlesh is currently also co-chairing the Schema Working Group in IP-XACT TC at Accellera System Initiative to work closely with other partners from semiconductor and EDA industry for enhancement, marketing and deployment of IP-XACT standard, as well as representing ST Microelectronics in the Accellera IP-XACT TC. Kamlesh has written several papers in the field of IP-XACT methodologies.
has 17 years of experience in digital, mixed signal, and analog baseband designs spanning semiconductor technologies from .6u to 28nm. ReUse "champion" within Philips, he managed the IC design team that implemented the Philips 3G modem and was a key contributor to the deployment of IP-XACT solutions since 2007 at the corporate level. He joined Magillem in 2011 as technical product manager for EDA solutions, bringing his vast IP-reuse expertise to Magillem’s product portfolio, contributing to major developments and impressive Magillem customer’s successful stories.