IEEE International Workshop on Design for Manufacturing and Yield (DFM&Y)
Monday, June 3, 2013
Time: 9:00 AM — 5:00 PM
Design for Manufacturability
|Organizer: ||Will Conley - Cymer, Inc., San Diego, CA|
|Speaker: ||Will Conley - Cymer, Inc., San Diego, CA|
Increased manufacturing susceptibility in today’s nanometer technologies requires up to date solutions for yield optimization. In fact, designing an SoC for manufacturability and yield aims at improving the manufacturing process and consequently its yield by enhancing communications across the design – manufacturing interface. A wide range of Design-for- Manufacturability (DFM), Design-for-Yield (DFY) and Design-for-Test (DFT) methodologies and tools are proposed today. Some of these are leveraged during the back-end design stages, and others have post design utilization, from lithography up to 3D integration, wafer sort, packaging, final test and failure analysis.
These solutions can dramatically impact the business performance of chip manufacturers. They can also significantly affect age-old chip design flows. Using a DFM/DFY/DFT solution is an investment and thus choosing the most cost effective one(s) requires trade-off analysis. The workshop will analyze key trends and challenges in DFM, DFY and DFT methodologies, and provide an opportunity to discuss a range of DFM, DFT and DFY solutions for SoC designs now and in the future, including practical case studies that demonstrate the successes and failures of such solutions.
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