register for dac
AUSTIN, TX | JUNE 2-6
Travel & Stay
DAC User Track
48th Call for Contributions
Students & Scholarships
PRESENTING YOUR WORK AT DAC
Sun. June 2
Mon. June 3
Tue. June 4
Wed. June 5
Thu. June 6
Designed in Texas
General Session/Award Presentations
New Challenges for Smarter Mobile Devices
VISIONARY TALK: Aart J. de Geus - Chairman and co-Chief Executive Officer, Synopsys, Inc.
What a Chip Designer Needs at the End of Moore's Law
Emerging Mapping and Management Algorithms for Parallel Embedded Systems
Answers to Some of Your Embedded System Design Questions
Better to be Proactive or be a Slacker in NoC Design?
Lay it out, Analog!
Don't Fret About Your FinFet: Physical Design in 14nm and Beyond
Emerging Application-Oriented, Low-Power Techniques
Transformations in FPGA Design and Productivity
Taming the Beast: Coping with Imperfect Design and Silicon Defects
Enlarging the Universe: Innovative Exploration for RTL and High-Level Synthesis
Teaching the Old Backend Compiler Dog New Tricks
Off-the-Shelf Techniques for Quantum and Bio Circuits
Designing and Modeling Biology Continues: Hurdles and Progress
Balancing Security and Utility in Medical Devices
The Silicon Flashlight: Mapping the Road to 6nm
My IP is Better than Yours, but Does Anyone Care?
System Design Approaches
Poster Session 1
Back-End Flows and Methodologies
New Uses of Formal Methods
Physical Design I
Physical Design II
Design Methodologies from ESL to Fault-Tolerance
Advanced Node Reliability: Are We in Trouble?
I Blew My Power Budget: Whom Should I Throw Under the Bus?
Is Security the Next Design Dimension?
Hogan’s Heroes: The EDA Hunger Games!
Great Expectations: Analog Mixed Signal Spectacle at the Design Border
Organizational and Management Solutions to the Verification Crisis
Is This the Right Time to Create Standards for 2.5D/3D-IC Designs?
Hardware-Assisted Development in 10 Years: More Need, More Speed
DAC Management Day 2013
A. Richard Newton Young Student Fellow Program
Customer Insights: Success with Synopsys Galaxy Implementation Platform
Synopsys Partner Breakfast: Ready for Deploying GLOBALFOUNDRIES’ 14xm FINFETS in Mobile SoC Design
26th ACM SIGDA University Booth at the 50th Design Automation Conference
The Cadence System-to-Silicon Verification Breakfast
CUSTOM DESIGN LUNCH: ADDRESSING CUSTOM DESIGN CHALLENGES WITH LAKER
Synopsys Lunch: SoC Leaders Verify with Synopsys
IEEE CEDA Presents: Cyber-Physical Systems: A Rehash or A New Intellectual Challenge?
IPL Alliance Dinner: IPDKS: A Thriving PDK Standard
SIGDA EC Meeting
© 2012 ACM/EDAC/IEEE Design Automation Conference. All rights reserved.
Website maintained by
MP Associates, Inc.