Bypass logic verification is a common and difficult challenge for modern VLSI design that arises in the verification of CPU, GPU, and networking ASICs. Get it wrong and/or miss a bug in the bypass logic and whole system can simply freeze.
Fortunately, the 2012 DAC User Track Best Presentation award-winning paper titled "Deploying Model Checking for Bypass Verification" by engineers from Cisco and Oski Technology (full citation below) describes an easily replicated, nearly push-button flow that does not require users to put in a lot of effort to write complex input constraints. And full disclosure: they used my favorite combined simulation+formal tool, Incisive Enterprise Verifier (IEV)!
Full Article
