Power continues to be the big issue at this year’s DAC, and it’s one of the primary focal points for announcements at this year’s conference in Austin, Texas.
Jasper Design, for example, just added power awareness to its formal verification tools. Formal is effective in routing out very specific design problems rather than verifying an entire SoC or even a block. Oz Levia, vice president of marketing at the company, explained that the goal is to take RTL and infuse it with power structure sequences, insert buffers and then extract assertions to verify the power sequencing is correct.
Full Article: Low-Power High-Performance Engineering Community