· Daily Matrices · DAC Pavilion Panels · Management Day@DAC · Wireless Wednesday · Search the Program · Keynotes · Papers · Panels · Special Sessions · Monday Tutorial · Friday Tutorials · Intro to EDA · Integrated Design Systems Workshop · UML for SoC Design · Women's Workshop · RTL Handoff · Core-based SoC Design	TUESDAY, June 14, 2005, 8:30 AM - 10:15 AM | Room: Ballroom ABC    KEYNOTE    How Does One Define "Technology" Now That Classical Scaling Is Dead (and Has Been for Years)?      Over the past four decades, the IT industry has relied upon the classical scaling of semiconductor technology to drive both performance and product economics. Often confused with Moore's Law, classical scaling speaks to the science driving performance gains over the past decades, not the subset economic issue addressing the real density of transistors on a chip. In effect, classical scaling had been the "glue" binding microprocessor economics, as stated by Moore's Law, to expectations for ongoing progress in microprocessor performance. The impact of the loss of that linkage with the demise of classical scaling has yet to be fully comprehended. The discontinuity engendered by the failure of classical scaling has shaken the microprocessor and IT industry to its foundation, forcing radical shifts in product roadmaps and business focus for those unprepared. This talk will briefly review the origins of this discontinuity, but more critically emphasize new strategies, such as Holistic Design, as employed to drive continued progress in IT performance. First results of the movement to Holistic Design, at chip and system level, will be reviewed, as will strategies meant to accelerate efforts in this vein.    Speaker(s): Bernard S. Meyerson - IBM Corp.