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TUESDAY, June 14, 2005, 2:00 PM - 4:00 PM | Room: 207D |
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TOPIC AREA: BUSINESS
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SESSION 100
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| | Choosing Flows and Methodologies for SoC Design
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| | Chair: Dennis C. Wassung, Jr. - Adams Harkness, Inc., Boston, MA
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| | Organizers: Yervant Zorian, Virage Logic
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| | Moving to new semiconductor technology nodes can dramatically impact the business performance of the SoC company, and its age-old design and manufacturing flows and methodologies. It can also significantly affect its choices of suppliers. This session will provide an overview of changing needs and corresponding management decision criteria to make the right choices from a pool of alternate options.
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| |  100.1 |
EDA Flows: Best-of-Breed or Single-Vendor Solution?
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| | Speaker(s): | Magdy Abadir - Freescale Semiconductor, Inc., Austin, TX
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| | 100.2 | The Criteria to Select: ASIC vs. Foundry Model |
| | Speaker(s): | Jeffery Kohlman - Freescale Semiconductor, Inc., Rolling Meadows, IL
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| | 100.3 | How to Choose from All the Process Nodes, IP Cores, and Other SoC Suppliers |
| | Speaker(s): | Norbert Diesing - PMC-Sierra, Inc, Burnaby, BC
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| | 100.4 | Soft Errors: Do You Need to Worry, and When? Which Applications are Affected? |
| | Speaker(s): | Kee Sup Kim - Intel Corp., Sacramento, CA
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