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| WEDNESDAY, June 15, 2005, 4:30 PM - 6:30 PM | Room: 207ABC | ||
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TOPIC AREA: SYSTEM-LEVEL DESIGN AND VERIFICATION (methods) | ||
| SESSION 31 | |||
| PANEL: Is Methodology the Highway Out of Verification Hell? | |||
| Chair: Gabe Moretti - Consultant, Venice, FL | |||
| Organizers: Francine Bacchini | |||
| Few would disagree that verification takes the lion's share of today's project resources. Given verification's tremendous burden and its painful impact on fundamental design quality and time-to-market demands, what is our industry doing in response? This panel explores where the methodology highway is taking us--is the destination heaven or just another level of Dante's inferno? | |||
 31.1 |
PANEL: Is Methodology the Highway Out of Verification Hell? |
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| Speaker(s): | Harry Foster - Jasper Design Automation, Mountain View, CA Janick Bergeron - Synopsys, Inc., Ottawa, ON, Canada Masayuki Nakamura - Sony Corp., Tokyo, Japan Shrenik Mehta - Sun Microsystems, Sunnyvale, CA Laurent Ducousso - STMicroelectronics, Grenoble Cedex, France | ||
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