CONVENED TUESDAY June 10, 4:30pm - 6:00pm | 206AB
TOPIC AREA: STRICTLY DESIGN
SESSION 13
IDESIGN: iDesign II
Chair: Ali El-Zein - IBM Corp., Austin, TX
Organizer: Leon Stok - IBM Corp., Hopewell Junction, NY
This iDesign session addresses practical aspects of designing using SystemVerilog. Experienced design consultants and users will give extensive examples on how to capitalize on several of the language features and unlayer the intimacies of the class libraries build on top of SystemVerilog. The first presentation addresses the new implicit port instantiation enhancements that help accelerate top-level composition of large ASIC and FPGA Designs. The second presentation focuses on the class libraries in SystemVerilog that enhance productivity. Both the VMM on OVM methodologies will be discussed and important differences pointed out. It will be described how to convert between the two, where this is straight forward and which aspects require more attention.
| 13.1 | SystemVerilog Implicit Port Enhancements Accelerate System Design & Verification | |
| Speaker: | Cliff Cummings - Sunburst Designs, Inc., Beaverton, OR |
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| Author: | Cliff Cummings - Sunburst Designs, Inc., Beaverton, OR |
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| 13.2 | Translation of an Existing VMM-based SystemVerilog Testbench to OVM | |
| Speaker: | Kelly Larson - MediaTek Wireless, Inc., Austin, TX |
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| Author: | Kelly Larson - MediaTek Wireless, Inc., Austin, TX |
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