CONVENED MONDAY June 09, 9:00am - 5:00pm | 209AB
MONDAY TUTORIAL: #2 - Programming Massively Parallel Processors: the NVIDIA Experience
Organizer: Diana Marculescu - Carnegie Mellon Univ., Pittsburgh, PA
This tutorial is meant to be a six hour accelerated course on software development for modern computer architectures with emphasis on the NVIDIA processors and the CUDA (Compute Unified Device Architecture) programming tools. Virtually all semiconductor market domains, including PCs, game consoles, mobile handsets, servers, supercomputers, and networks, are converging to concurrent platforms. There are two important reasons for this trend. First, these concurrent processors can potentially offer more effective use of chip space and power than traditional monolithic microprocessors for many demanding applications. Second, an increasing number of applications that traditionally used Application Specific Integrated Circuits (ASICs) are now implemented with concurrent processors in order to improve functionality and reduce engineering cost. The real challenge is to develop applications software that effectively uses these concurrent processors to achieve efficiency and performance goals.
The aim of this tutorial is to provide attendees with knowledge necessary for developing applications software for processors with massively parallel computing resources. Effectively programming these processors will require in-depth knowledge about parallel programming principles, as well as the parallelism models, communication models, and resource limitations of these processors. The target audiences of the course are professionals who want to develop exciting applications for these processors, as well as those who want to develop programming tools and future implementations for these processors. The tutorial will also explore the use of such processors for EDA applications.
Wen-mei W. Hwu is a Professor and holds the Walter J. ("Jerry") Sanders III-Advanced Micro Devices Endowed Chair in Electrical and Computer Engineering of the University of Illinois at Urbana-Champaign. His research interests are in the area of architecture, implementation, and compilation for parallel computer systems. He is the director of the IMPACT research group (www.crhc.uiuc.edu/Impact). For his contributions in research and teaching, he received the ACM SIGARCH Maurice Wilkes Award, the ACM Grace Murray Hopper Award, the Tau Beta Pi Daniel C. Drucker Eminent Faculty Award, and the ISCA Most Influential Paper Award. He is a fellow of IEEE and ACM. Hwu serves on the Executive Committee of the MARCO/DARPA C2S2 (www.c2s2.org) and GSRC (www.gigascale.org) Focus Research Centers. He leads the GSRC Concurrent Systems Theme. He is the hardware lead of the $208M NSF Petascale Computer Project awarded to the University of Illinois and IBM in 2007. He also serves on the GELATO Strategy Council (www.gelato.org). Dr. Hwu received his Ph.D. degree in Computer Science from the University of California, Berkeley.
David Kirk has been NVIDIA's Chief Scientist since January 1997. His contribution includes leading NVIDIA graphics technology development for today’s most popular consumer entertainment platforms. In 2007, Dr. Kirk was elected to the National Academy of Engineering (NAE) for his role in bringing high-performance graphics to personal computers. Election to the NAE is among the highest professional distinctions awarded in engineering. In 2002, Dr. Kirk received the ACM SIGGRAPH Computer Graphics Achievement Award for his role in bringing high-performance computer graphics systems to the mass market. From 1993 to 1996, Dr. Kirk was Chief Scientist, Head of Technology for Crystal Dynamics, a video game manufacturing company. From 1989 to 1991, Dr. Kirk was an engineer for the Apollo Systems Division of Hewlett-Packard Company. Dr. Kirk is the inventor of 50 patents and patent applications relating to graphics design and has published more than 50 articles on graphics technology. Dr. Kirk holds B.S. and M.S. degrees in Mechanical Engineering from the Massachusetts Institute of Technology and M.S. and Ph.D. degrees in Computer Science from the California Institute of Technology.
Damir Jamsek is Research Staff Member at IBM Austin Research Lab where he has worked on hardware design, verification and cad tool development. He has lead groups developing high-speed arithmetic (>8GHZ multipliers) and memory circuits (~6GHZ SRAM). His interest in GPGPU computing is driven by the possibility of orders of magnitude speed-up in CAD algorithms that are currently in use by IBM processor development teams where day and week long runs are typical. Damir received his Ph.D. from the Department of Electrical and Computer Engineering at Syracuse University in 1990. He was a research staff member at the Microelectronics and Computer Corporation (MCC) and held the position of chief scientist at Odyssey Research Associates (ORA) prior to joining IBM.
David Kirk - NVIDIA Corp., Santa Clara, CA
Damir A. Jamsek - IBM Corp., Austin, TX