CONVENED TUESDAY June 10, 4:30pm - 6:00pm | 208AB
TOPIC AREA: VERIFICATION AND TEST
SESSION 15
REGULAR SESSION: Experiences and Advances in Formal and Dynamic Verification
Chair: Maruthy Vedam - Qualcomm, Inc., San Diego, CA
In the first paper in this session, a methodology is presented for identifying challenging parts of a design and improving their verifiability. The second paper introduces a method for compressing test cases based on machine learning with the hope of improving the speed of coverage convergence. In the third paper, the authors present their experience of applying assertion-based verification to a microprocessor. The fourth and final paper suggests to pipeline emulation to speed up dynamic verification.
| 15.1 | Assertion Based Verification of a 32 Thread SPARC CMT Microprocessor | |
| Speaker: | Babu Turumella - Sun Microsystems, Inc., Santa Clara, CA |
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| Authors: | Babu Turumella - Sun Microsystems, Inc., Santa Clara, CA Mukesh Sharma - Sun Microsystems, Inc., Santa Clara, CA |
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| 15.2 | Functional Test Selection Based on Unsupervised Support Vector Analysis | |
| Speaker: | Onur Guzey - Univ. of California, Santa Barbara, CA |
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| Authors: | Onur Guzey - Univ. of California, Santa Barbara, CA Li-C. Wang - Univ. of California, Santa Barbara, CA Jeremy Levitt - Mentor Graphics Corp., San Jose, CA Harry Foster - Mentor Graphics Corp., San Jose, CA |
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| 15.3s | Early Formal Verification of Conditional Coverage Points to Identify Intrinsically Hard-to-verify Logic | |
| Speaker: | Michael Theobald - D. E. Shaw Research, New York, NY |
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| Authors: | C. Richard Ho - D. E. Shaw Research, Cupertino, CA Michael Theobald - D. E. Shaw Research, New York, NY Martin M. Deneroff - D. E. Shaw Research, New York, NY Ron O. Dror - D. E. Shaw Research, New York, NY Joseph Gagliardo - D. E. Shaw Research, New York, NY David E. Shaw - D. E. Shaw Research, New York, NY |
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