CONVENED MONDAY June 09, 8:30am - 4:30pm | 212A
WORKSHOP: Cross-layer Power and Thermal Management
Yung-Hsiang Lu - Purdue Univ., West Lafayette, IN
Reducing power consumption and managing temperature have become two most critical issues in electronic designs. This is reflected in the topics of many conference and journal papers. However, there are insufficient opportunities for researchers in different areas to interact. This workshop will serve the purpose of “creating conversations” among researchers with different backgrounds. A wide range of topics are covered in this workshop; the topics are divided into five different layers: circuits and devices, packaging, architectures, systems, and software design. Five experts, from academia and industry, are invited to present their views on existing solutions and future challenges in power and thermal management. Each speaker will explain the state-of-the-art technology, relationships and interactions with other layers in electronic design, and point out directions for future research. This workshop is the first of its kind and will bring together many researchers from different areas to develop new visions for research on power and thermal management.
The workshop is partially sponsored by the Low Power Technical Committee of ACM Special Interest Group on Design Automation (SIGDA).
8:30-8:50am Breakfast
8:50-9:00am Welcome: Yung-Hsiang Lu and Ricardo Bianchini
9:00-9:45am Session 1: Low-Voltage Low-Power CMOS: Device & Circuit Perspective
Chair: Barry Pangrle, Consultant, San Jose, CA
Supply voltage scaling is one of the most effective ways to reduce power dissipation in CMOS circuits. In this talk I will present voltage over-scaling to reduce total power dissipation while still being able to maintain high throughput. The implications of such an approach at the device, circuit and architectural level will be considered. Finally, a design technique for ultra low voltage (below or near threshold) robust circuits will be presented.
Speaker: Kaushik Roy, Purdue Univ., West Lafayette, IN
Kaushik Roy received B.Tech. degree in electronics and electrical communications engineering from the Indian Institute of Technology, Kharagpur, India, and Ph.D. degree from the electrical and computer engineering department of the University of Illinois at Urbana-Champaign in 1990. He was with the Semiconductor Process and Design Center of Texas Instruments, Dallas, TX, where he worked on FPGA architecture development and low-power circuit design. He joined the electrical and computer engineering faculty at Purdue University, West Lafayette, IN, in 1993, where he is currently a Professor and holds the Roscoe H. George Chair of Electrical & Computer Engineering. His research interests include VLSI design/CAD for nano-scale Silicon and non-Silicon technologies, low-power electronics for portable computing and wireless communications, VLSI testing and verification, and reconfigurable computing. Dr. Roy has published more than 450 papers in referred journals and conferences, holds 8 patents, and is co-author of two books on Low Power CMOS VLSI Design (John Wiley & McGraw Hill).
Roy received the National Science Foundation Career Development Award in 1995, IBM faculty partnership award, ATT/Lucent Foundation award, 2005 SRC Technical Excellence Award, SRC Inventors Award, Purdue College of Engineering Research Excellence Award, and best paper awards at 1997 International Test Conference, IEEE 2000 International Symposium on Quality of IC Design, 2003 IEEE Latin American Test Workshop, 2003 IEEE Nano, 2004 IEEE International Conference on Computer Design, 2006 IEEE/ACM International Symposium on Low Power Electronics & Design, and 2005 IEEE Circuits and system society Outstanding Young Author Award (Chris Kim), 2006 IEEE Transactions on VLSI Systems best paper award. Roy is Purdue University Faculty Scholar. Roy is the Chief Technical Advisor of Zenasis Inc. and Research Visionary Board Member of Motorola Labs (2002). He has been in the editorial board of IEEE Design and Test, IEEE Transactions on Circuits and Systems, and IEEE Transactions on VLSI Systems. He was Guest Editor for Special Issue on Low-Power VLSI in the IEEE Design and Test (1994) and IEEE Transactions on VLSI Systems (June 2000), IEE Proceedings- Computers and Digital Techniques (July 2002). Roy is a fellow of IEEE.
9:45-10:30am Session 2: System on Package (SoP): A Platform for Micro, Nano and Bio Convergence
Chair: Robert P. Dick, Northwestern Univ., Evanston, IL
As the semiconductor industry moves beyond the 45nm node and as systems become more heterogeneous, System on Chip (SoC) solutions are facing major barriers due to technical and business related reasons. This is leading to the development of new technological solutions such as System on Package (SoP). SoP, a technology being pioneered by Georgia Tech, allows for integration of functions in the package. Higher levels of integration are possible by embedding functions in the substrate and merging the package and board level technologies into one. SoP enables the integration of digital, RF, opto-electronic and sensor electronics in the package leading to system miniaturization with micro, nano and bio convergence. This solution offers advantages for power and thermal management as well, which will be discussed in this presentation.
Speaker: Madhavan Swaminathan, Georgia Tech., Atlanta, Georgia
Madhavan Swaminathan is the Joseph M. Pettit Professor in Electronics in the School of Electrical and Computer Engineering and Deputy Director of the Microsystems Packaging Research Center, Georgia Tech. He is the co-founder of Jacket Micro Devices, a company specializing in RF substrates and modules for WLAN and WiMAX applications and SoPWorX, a developer of EDA tools for System on Package technologies. He has over 300 publications in referred journals and conferences, 15 patents and is the author and co-editor of two books "Power Integrity Modeling and Design for Semiconductors and Systems", Prentice Hall, Nov 2007 and "Introduction to SOP", McGraw Hill, 2008. Prior to joining Georgia Tech, he was with IBM working on the packaging for supercomputers. Madhavan is a Fellow of IEEE and is one of the pioneers of SOP technology at Georgia Tech.
10:30-11:00am Break
11:00-11:45am Session 3: Multi-core and Energy
Chair: Tajana Simunic Rosing, Univ. of California, San Diego, La Jolla, CA
This talk discusses the factors that determine energy per instruction in a microprocessor: design, process technology, and environment. We present a historical view of energy per instruction trends in Intel microprocessors and show that significantly lower energy per instruction can be achieved by multi-core processors compared to previous-generation uniprocessors. We also demonstrate the performance advantages of dynamically varying a processor's energy per instruction according to the amount of parallelism available in the workload.
Speaker: Edward Grochowski, Intel Corp., Santa Clara, CA
Ed Grochowski is a Senior Principal Engineer at Intel Corporation in Santa Clara, California. Ed joined Intel in 1986 and has had various technical and managerial responsibilities in the Intel i486, Pentium, Pentium II, and Itanium microprocessor design teams. He worked on microarchitectural techniques for energy-efficient chip multiprocessors in Intel's Microprocessor Research Labs, and is currently working on the design of a future graphics processor. Ed received his B.S.E.E. and his M.S.E.E. from the University of California, Berkeley.
11:45am-12:30pm Session 4: Power Management: A System-Level Concern Demanding System- Wide Solutions
Chair: Eugene Gorbatov, Intel Corp., Santa Clara, CA
The presentation will outline why power management is an integral part of systems management and has become a driver of systems design. It will address the different requirements for power management from a computer systems perspective and why the solutions need to be driven by system-level concerns. And how system-level approaches deal with and pull together all the elements across the stack to provide complete power management solutions. The presentation will also discuss different challenges in delivering system-wide solutions and availability of what technologies and capabilities might help.
Speaker: Karthick Rajamani, IBM Corp., Austin, Texas
Bio: Karthick Rajamani is a Research Staff Member in the IBM Austin Research Lab working on computer systems design and technologies for performance and power management. He received his Bachelors degree from the Indian Institute of Technology, Madras, and his MS and PhD from Rice University, Houston, TX. His current interests include memory systems design, adaptive application-aware power management solutions and power management solutions for datacenters.
12:30-2:00pm Lunch, Room 212B
2:00-2:45pm Session 5: Abstracting Physical Effects
Chair: Yuan Xie, Penn State Univ., University Park, PA
There is currently no direct abstraction for physical effects like temperature.However thermal management has a high impact on the execution behavior of higher software levels. This talk discusses the requirements for the hardware/software interface to allow temperature-aware system-level policies in an energy-aware cross-layer design.
Speaker: Frank Bellosa, Univ. of Karlsruhe, Karlsruhe, Germany
Frank Bellosa received his PhD in computer science from the University of Erlangen in 1998. He worked in the systems development of Siemens Communication Networks and joined the OS group of the University of Erlangen as assistant professor in 1999. Since December 2004 Frank Bellosa is full professor and head of the System Architecture Group at the Department of Computer Science of the University of Karlsruhe. His principal field of interest is design and building of operating systems. Currently he is working on OS-directed power management for energy-aware systems. He served on the program committee of ASPLOS, PACT, ISLPED, TACS, HPPAC, USENIX, and EuroSys. At present he is ACM SIGOPS Vice Chair.
2:45-3:55pm Panel Session
Moderator: Yung-Hsiang Lu
Panelists: Kaushik Roy, Madhavan Swaminathan, Edward Grochowski, Karthick Rajamani, Frank Bellosa
3:55-4:00pm Break
4:00-4:25pm ACM SIGDA LPTC
ACM Low-Power Technical Committee (LPTC) is one of the SIGDA Technical Committees that focus on the low-power systems design. This talk will introduce the plans, activities, organization, website and bylaw of LPTC. The LPTC (Low-Power Technical Committee) performs range of activities to promote the low-power systems research speaking voice for the interest of LPTC, providing links between academia and industries, supporting low-power research activities, educating low-power systems researchers and students, etc.
Speaker: Naehyuck Chang, Seoul National Univ., Seoul, Republic of Korea
Naehyuck Chang received his BS, MS and PhD degrees all from Seoul National University, in 1989, 1992 and 1996, respectively. He joined Seoul National University in Dept. of Computer Science and Engineering in 1997 as a faculty member and now is an Associate Professor in the Dept. of Electrical Engineering and Computer Science. He serves (and served) on the Technical Program Committee of ACM SIGDA and IEEE Circuits and Systems Society conferences and symposiums such as DAC, ICCAD, ISLPED, ISQED, ACM GLSVLSI, ASP-DAC, CODES+ISSS, and sister workshops such as PATMOS, ESTIMedia, and so on. He also serves as Committee Member of ACM SIGDA PhD Forum, ACM/IEEE ASP-DAC PhD Forum, and SIGDA Graduate Scholarship. In 2007, he served as the Technical Program Chair of RTCSA 2007. He served as an organizing committee member of AP-ASIC 2000, ESWeek 2006 and ASP-DAC 2008. He is an associate editor of IEEE TCAD for 2006 to 2008, and editorial board members of Journal of Low-Power Electronics and Journal of Embedded Computing. He is currently the Chair of ACM SIGDA Low-Power Technical Committee. He is a Senior Member of ACM and a Senior Member of IEEE.
4:25-4:30pm Closing Remarks: Yung-Hsiang Lu and Ricardo Bianchini
Naehyuck Chang - Seoul National Univ., Seoul, Republic of Korea
Edward Grochowski - Intel Corp., Santa Clara, CA
Karthick Rajamani - IBM Corp., Austin, TX
Kaushik Roy - Purdue Univ., West Lafayette, IN
Madhavan Swaminathan - Georgia Institute of Technology, Atlanta, GA