CONVENED TUESDAY June 10, 2:00pm - 4:00pm | 208AB
TOPIC AREA: VERIFICATION AND TEST
SESSION 9
REGULAR SESSION: Formal Verification Technology
Chair: Ziyad Hanna - Jasper Design Automation, Inc., Mountain View, CA
A core challenge with formal verification is always scalability to large designs. This session presents four papers that advance the state-of-the-art in formal verification technology, making formal verification tools more efficient and usable.
| 9.1 | Compositional Verification of Retiming and Sequential Optimizations | |
| Speaker: | In-Ho Moon - Synopsys, Inc., Hillsboro, OR |
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| Author: | In-Ho Moon - Synopsys, Inc., Hillsboro, OR |
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| 9.2 | Tunneling and Slicing: Towards Scalable BMC | |
| Speaker: | Malay Ganai - NEC Corp., Princeton, NJ |
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| Authors: | Malay Ganai - NEC Corp., Princeton, NJ Aarti Gupta - NEC Corp., Princeton, NJ |
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| 9.3 | Optimizing Automatic Abstraction Refinement for Generalized Symbolic Trajectory Evaluation | |
| Speaker: | Yan Chen - Portland State Univ., Portland, OR |
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| Authors: | Yan Chen - Portland State Univ., Portland, OR Fei Xie - Portland State Univ., Portland, OR Jin Yang - Intel Corp., Hillsboro, OR |
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| 9.4 | Faster Symmetry Discovery Using Sparsity of Symmetries | |
| Speaker: | Paul T. Darga - Univ. of Michigan, Ann Arbor, MI |
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| Authors: | Paul T. Darga - Univ. of Michigan, Ann Arbor, MI Karem A. Sakallah - Univ. of Michigan, Ann Arbor, MI Igor L. Markov - Univ. of Michigan, Ann Arbor, MI |
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