Functional Verification
MONDAY - November 02, 11:00am - 12:30pm / Oak
Scheduling Techniques for Low Power
MONDAY - November 02, 11:00am - 12:30pm / Cedar
Advances in Routing
MONDAY - November 02, 11:00am - 12:30pm / Fir
Analysis and Mitigation of Transient and Permanent Failures
MONDAY - November 02, 2:00pm - 4:00pm / Cedar
Advances in Test Efficiency
MONDAY - November 02, 2:00pm - 4:00pm / Oak
Design Automation for Biological Systems
MONDAY - November 02, 2:00pm - 4:00pm / Pine
Advances in FPGA Synthesis and Trustable Silicon
MONDAY - November 02, 2:00pm - 4:00pm / Fir
Emerging Design and Memory Technologies
MONDAY - November 02, 4:30pm - 6:00pm / Cedar
Routing in Alternative Technologies
MONDAY - November 02, 4:30pm - 6:00pm / Pine
Timing Closure and Design Robustness
MONDAY - November 02, 4:30pm - 6:00pm / Fir
Emerging Topics in Test and Reliability
MONDAY - November 02, 4:30pm - 6:00pm / Oak
Thermal-Aware Management Techniques for Multi-Core Architectures
TUESDAY - November 03, 8:30am - 10:00am / Pine
Analytical Advances in Physical Synthesis
TUESDAY - November 03, 8:30am - 10:00am / Fir
New Applications in Logic Synthesis
TUESDAY - November 03, 10:30am - 12:00pm / Pine
Congestion Driven Placement
TUESDAY - November 03, 10:30am - 12:00pm / Fir
Statistical Timing Analysis and Its Application
TUESDAY - November 03, 10:30am - 12:00pm / Oak
Characterization and Compensation of Variability
TUESDAY - November 03, 1:30pm - 3:30pm / Fir
Emerging Memory Technologies
TUESDAY - November 03, 1:30pm - 3:30pm / Cedar
Advanced Modeling and Simulation Methods
TUESDAY - November 03, 1:30pm - 3:30pm / Oak
Policies and Methods for Low Power
TUESDAY - November 03, 1:30pm - 3:30pm / Pine
Advanced Device Reliability and Modeling
TUESDAY - November 03, 4:00pm - 6:00pm / Oak
Clock Optimization and Parallel Algorithm in EDA
TUESDAY - November 03, 4:00pm - 6:00pm / Fir
Design-Patterning Interactions
TUESDAY - November 03, 4:00pm - 6:00pm / Cedar
Analysis and Optimization of Network-On-Chip and Multiprocessor SOC
TUESDAY - November 03, 4:00pm - 6:00pm / Pine
Yield Estimation and Optimization for SRAMs
WEDNESDAY - November 04, 8:30am - 10:00am / Oak
Analytic Placement
WEDNESDAY - November 04, 8:30am - 10:00am / Pine
Performance and Power Issues in Embedded System-Level Design
WEDNESDAY - November 04, 8:30am - 10:00am / Cedar
Thermal Modeling and Analysis at Chip and Platform Levels
WEDNESDAY - November 04, 8:30am - 10:00am / Fir
Statistical Simulation and Optimization of Serial Link and Wordlength
WEDNESDAY - November 04, 10:30am - 12:30pm / Oak
Parasitic Extraction, Modeling, and Reduction Techniques
WEDNESDAY - November 04, 10:30am - 12:30pm / Fir
Advanced Boolean Techniques in Logic Synthesis
WEDNESDAY - November 04, 10:30am - 12:30pm / Pine
MONDAY - November 02, 11:00am - 12:30pm / Oak
Scheduling Techniques for Low Power
MONDAY - November 02, 11:00am - 12:30pm / Cedar
Advances in Routing
MONDAY - November 02, 11:00am - 12:30pm / Fir
Analysis and Mitigation of Transient and Permanent Failures
MONDAY - November 02, 2:00pm - 4:00pm / Cedar
Advances in Test Efficiency
MONDAY - November 02, 2:00pm - 4:00pm / Oak
Design Automation for Biological Systems
MONDAY - November 02, 2:00pm - 4:00pm / Pine
Advances in FPGA Synthesis and Trustable Silicon
MONDAY - November 02, 2:00pm - 4:00pm / Fir
Emerging Design and Memory Technologies
MONDAY - November 02, 4:30pm - 6:00pm / Cedar
Routing in Alternative Technologies
MONDAY - November 02, 4:30pm - 6:00pm / Pine
Timing Closure and Design Robustness
MONDAY - November 02, 4:30pm - 6:00pm / Fir
Emerging Topics in Test and Reliability
MONDAY - November 02, 4:30pm - 6:00pm / Oak
Thermal-Aware Management Techniques for Multi-Core Architectures
TUESDAY - November 03, 8:30am - 10:00am / Pine
Analytical Advances in Physical Synthesis
TUESDAY - November 03, 8:30am - 10:00am / Fir
New Applications in Logic Synthesis
TUESDAY - November 03, 10:30am - 12:00pm / Pine
Congestion Driven Placement
TUESDAY - November 03, 10:30am - 12:00pm / Fir
Statistical Timing Analysis and Its Application
TUESDAY - November 03, 10:30am - 12:00pm / Oak
Characterization and Compensation of Variability
TUESDAY - November 03, 1:30pm - 3:30pm / Fir
Emerging Memory Technologies
TUESDAY - November 03, 1:30pm - 3:30pm / Cedar
Advanced Modeling and Simulation Methods
TUESDAY - November 03, 1:30pm - 3:30pm / Oak
Policies and Methods for Low Power
TUESDAY - November 03, 1:30pm - 3:30pm / Pine
Advanced Device Reliability and Modeling
TUESDAY - November 03, 4:00pm - 6:00pm / Oak
Clock Optimization and Parallel Algorithm in EDA
TUESDAY - November 03, 4:00pm - 6:00pm / Fir
Design-Patterning Interactions
TUESDAY - November 03, 4:00pm - 6:00pm / Cedar
Analysis and Optimization of Network-On-Chip and Multiprocessor SOC
TUESDAY - November 03, 4:00pm - 6:00pm / Pine
Yield Estimation and Optimization for SRAMs
WEDNESDAY - November 04, 8:30am - 10:00am / Oak
Analytic Placement
WEDNESDAY - November 04, 8:30am - 10:00am / Pine
Performance and Power Issues in Embedded System-Level Design
WEDNESDAY - November 04, 8:30am - 10:00am / Cedar
Thermal Modeling and Analysis at Chip and Platform Levels
WEDNESDAY - November 04, 8:30am - 10:00am / Fir
Statistical Simulation and Optimization of Serial Link and Wordlength
WEDNESDAY - November 04, 10:30am - 12:30pm / Oak
Parasitic Extraction, Modeling, and Reduction Techniques
WEDNESDAY - November 04, 10:30am - 12:30pm / Fir
Advanced Boolean Techniques in Logic Synthesis
WEDNESDAY - November 04, 10:30am - 12:30pm / Pine
