DAC 2010 ANAHEIM JUNE 13-18
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DAC Archive

Session 2: SPECIAL SESSION: Enabling Concurrency in EDA
TUESDAY - June 10, 10:30am - 12:00pm / 207ABC

Session 3: CAD for FPGA
TUESDAY - June 10, 10:30am - 12:00pm / 208AB

Session 4: Analog Performance Modeling and Synthesis
TUESDAY - June 10, 10:30am - 12:00pm / 209AB

Session 5: Novel Techniques in Embedded Processor Design
TUESDAY - June 10, 10:30am - 12:00pm / 210AB

Session 9: Formal Verification Technology
TUESDAY - June 10, 2:00pm - 4:00pm / 208AB

Session 10: Layout Techniques for Modern Chip Designs
TUESDAY - June 10, 2:00pm - 4:00pm / 209AB

Session 11: Application Mapping and Power Efficiency
TUESDAY - June 10, 2:00pm - 4:00pm / 210AB

Session 12: Variation-aware Design
TUESDAY - June 10, 2:00pm - 4:00pm / 210CD

Session 14: Multi-core Simulation, Mixed-signal Power Optimization and Nanodevices
TUESDAY - June 10, 4:30pm - 6:00pm / 207ABC

Session 15: Experiences and Advances in Formal and Dynamic Verification
TUESDAY - June 10, 4:30pm - 6:00pm / 208AB

Session 16: Emerging Nano/Biotechnologies
TUESDAY - June 10, 4:30pm - 6:00pm / 209AB

Session 17: Cache Optimization and Embedded Systems Modeling
TUESDAY - June 10, 4:30pm - 6:00pm / 210AB

Session 19: Analytical Modeling and Simulation of Complex Processing Systems
WEDNESDAY - June 11, 9:00am - 11:00am / 206AB

Session 22: Diagnosis and Debug
WEDNESDAY - June 11, 9:00am - 11:00am / 209AB

Session 23: Architectural and Precision Optimization in High-level Synthesis
WEDNESDAY - June 11, 9:00am - 11:00am / 210AB

Session 24: Extraction, Interconnect and Timing
WEDNESDAY - June 11, 9:00am - 11:00am / 210CD

Session 25: Architectures for On-chip Communication
WEDNESDAY - June 11, 2:00pm - 4:00pm / 206AB

Session 27: Advanced Wireless Design
WEDNESDAY - June 11, 2:00pm - 4:00pm / 208AB

Session 28: Manufacturing Aware Design and Design Aware Manufacturing
WEDNESDAY - June 11, 2:00pm - 4:00pm / 209AB

Session 29: Advances in Sequential Optimization
WEDNESDAY - June 11, 2:00pm - 4:00pm / 210AB

Session 31: Beyond the Die - Packaging and Die Stacking
WEDNESDAY - June 11, 4:30pm - 6:00pm / 206AB

Session 34: Leakage Analysis and Optimization
WEDNESDAY - June 11, 4:30pm - 6:00pm / 209AB

Session 35: Design Methods for On-chip Communication
WEDNESDAY - June 11, 4:30pm - 6:00pm / 210AB

Session 37: New Advances in Logic Synthesis
THURSDAY - June 12, 9:00am - 11:00am / 206AB

Session 39: Statistical Timing Analysis
THURSDAY - June 12, 9:00am - 11:00am / 208AB

Session 40: Performance Driven Layout Optimization
THURSDAY - June 12, 9:00am - 11:00am / 209AB

Session 41: Power and Thermal Considerations in Single- and Multi-core Systems
THURSDAY - June 12, 9:00am - 11:00am / 210AB

Session 42: Multi-core Design Tools and Architectures
THURSDAY - June 12, 9:00am - 11:00am / 210CD

Session 43: Reconfigurable Architecture Optimizations
THURSDAY - June 12, 2:00pm - 4:00pm / 206AB

Session 45: Random Topics in Testing
THURSDAY - June 12, 2:00pm - 4:00pm / 208AB

Session 46: Securing and Debugging Embedded Systems
THURSDAY - June 12, 2:00pm - 4:00pm / 209AB

Session 47: Topics in Power and Thermal Management
THURSDAY - June 12, 2:00pm - 4:00pm / 210AB

Session 49: Physical Effects of Variability
THURSDAY - June 12, 4:30pm - 6:00pm / 206AB

Session 50: Soft Error in Scaled CMOS Design
THURSDAY - June 12, 4:30pm - 6:00pm / 207ABC

Session 51: Advances in Verification of Abstract (pre-RTL) Models
THURSDAY - June 12, 4:30pm - 6:00pm / 208AB

Session 52: Design Space Exploration
THURSDAY - June 12, 4:30pm - 6:00pm / 209AB

Session 53: Noise Reliability Enhancement
THURSDAY - June 12, 4:30pm - 6:00pm / 210AB

IEEE Solid State Circuits Society Electronic Design Automation Consortium CEDA - IEEE Council on Electronic Design Automation SIGDA Special Interest Group - Design Automation